This is an archived copy of the Xen.org mailing list, which we have preserved to ensure that existing links to archives are not broken. The live archive, which contains the latest emails, can be found at http://lists.xen.org/
Home Products Support Community News


Re: [Xen-devel] [PATCH] "lock cmpxch8b" and split locks

To: "Puthiyaparambil, Aravindh" <aravindh.puthiyaparambil@xxxxxxxxxx>
Subject: Re: [Xen-devel] [PATCH] "lock cmpxch8b" and split locks
From: Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>
Date: Fri, 7 Oct 2005 09:55:36 +0100
Cc: "Koren, Bradley J" <Bradley.Koren@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxx, "Subrahmanian, Raj" <raj.subrahmanian@xxxxxxxxxx>, "Vessey, Bruce A" <Bruce.Vessey@xxxxxxxxxx>
Delivery-date: Fri, 07 Oct 2005 08:48:06 +0000
Envelope-to: www-data@xxxxxxxxxxxxxxxxxxx
In-reply-to: <EF8D308BE33AF54D8934DF26520252D302CBC144@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>
List-help: <mailto:xen-devel-request@lists.xensource.com?subject=help>
List-id: Xen developer discussion <xen-devel.lists.xensource.com>
List-post: <mailto:xen-devel@lists.xensource.com>
List-subscribe: <http://lists.xensource.com/cgi-bin/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=subscribe>
List-unsubscribe: <http://lists.xensource.com/cgi-bin/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=unsubscribe>
References: <EF8D308BE33AF54D8934DF26520252D302CBC144@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>
Sender: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
Nice try, but the first sentence of your quote applies only to ordinary (non-LOCKed) memory accesses. Section states that "The integrity of a bus lock is not affected by the alignment of the memory field. The LOCK semantics are followed for as many bus cycles as necessary to update the entire operand."

I'm sure you get away with this in practise. 64-bit quantities are the only simple type that does not get naturally aligned in x86 C ABI. cmpxchg8b is a pretty rare instruction and most users would be very careful to ensure correct alignment in the cases it is used. Luckily it was easy for us to make the necessary changes too.

 -- Keir

On 6 Oct 2005, at 22:00, Puthiyaparambil, Aravindh wrote:

I spoke to our hardware engineers about this. They pointed me at Section
7.1.1 of Volume 3 of the Intel Software Developers Manual.

"Accesses to cacheable memory that are split across bus widths, cache
lines, and page boundaries are not guaranteed to be atomic by the
Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The
Pentium 4, Intel Xeon, and P6 family processors provide bus control
signals that permit external memory subsystems to make split accesses
atomic; however, on aligned data accesses will seriously impact the
performance of the processor and should be avoided."

I hope this gives you a better picture of the situation.

Xen-devel mailing list