[PATCH v4 21/28] x86emul: support AMX-FP8 insns

[Jan Beulich <jbeulich@xxxxxxxx>]

They can simply be wired into existing handling, and this feature can then
(optionally) be exposed to guests right away.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
v4: New.

--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -1522,6 +1522,11 @@ static const struct vex {
     { { 0xde }, 3, T, R, pfx_66, W0, L0 }, /* vsm3rnds2 */
     { { 0xdf }, 3, T, R, pfx_66, WIG, Ln }, /* vaeskeygenassist */
     { { 0xf0 }, 3, T, R, pfx_f2, Wn, L0 }, /* rorx */
+}, vex_map5[] = {
+    { { 0xfd, 0xc0 }, 2, F, N, pfx_no, W0, L0 }, /* tdpbf8ps */
+    { { 0xfd, 0xc0 }, 2, F, N, pfx_66, W0, L0 }, /* tdphf8ps */
+    { { 0xfd, 0xc0 }, 2, F, N, pfx_f3, W0, L0 }, /* tdphbf8ps */
+    { { 0xfd, 0xc0 }, 2, F, N, pfx_f2, W0, L0 }, /* tdpbhf8ps */
 }, vex_map7[] = {
     { { 0xf6, 0xc0 }, 6, F, N, pfx_f3, W0, L0 }, /* wrmsrns */
     { { 0xf6, 0xc0 }, 6, F, N, pfx_f2, W0, L0 }, /* rdmsr */
@@ -1537,7 +1542,7 @@ static const struct {
     { vex_0f38, ARRAY_SIZE(vex_0f38) },
     { vex_0f3a, ARRAY_SIZE(vex_0f3a) },
     { NULL,     0 }, /* map 4 */
-    { NULL,     0 }, /* map 5 */
+    { vex_map5, ARRAY_SIZE(vex_map5) },
     { NULL,     0 }, /* map 6 */
     { vex_map7, ARRAY_SIZE(vex_map7) },
 };
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -1532,6 +1532,23 @@ decode_map4(struct x86_emulate_state *s,
     return rc;
 }
 
+static int
+decode_map5(struct x86_emulate_state *s,
+            struct x86_emulate_ctxt *ctxt,
+            const struct x86_emulate_ops *ops)
+{
+    int rc = X86EMUL_OKAY;
+
+    switch ( ctxt->opcode & 0xff )
+    {
+    case 0xfd:
+        s->simd_size = simd_other;
+        break;
+    }
+
+    return rc;
+}
+
 #define ad_bytes (s->ad_bytes) /* for truncate_ea() */
 
 int x86emul_decode(struct x86_emulate_state *s,
@@ -1886,12 +1903,6 @@ int x86emul_decode(struct x86_emulate_st
                         break;
 
                     case evex_map5:
-                        if ( !evex_encoded() )
-                        {
-                    default:
-                            rc = X86EMUL_UNRECOGNIZED;
-                            goto done;
-                        }
                         opcode |= MASK_INSR(5, X86EMUL_OPC_EXT_MASK);
                         /*
                          * Re-use twobyte_table[] here, for the similarity of
@@ -1906,6 +1917,7 @@ int x86emul_decode(struct x86_emulate_st
                     case evex_map6:
                         if ( !evex_encoded() )
                         {
+                    default:
                             rc = X86EMUL_UNRECOGNIZED;
                             goto done;
                         }
@@ -2171,7 +2183,7 @@ int x86emul_decode(struct x86_emulate_st
             switch ( b )
             {
             default:
-                if ( s->evex.pfx != vex_f2 )
+                if ( evex_encoded() && s->evex.pfx != vex_f2 )
                     s->fp16 = true;
                 break;
 
@@ -2677,6 +2689,9 @@ int x86emul_decode(struct x86_emulate_st
         break;
 
     case ext_map5:
+        rc = decode_map5(s, ctxt, ops);
+        break;
+
     case ext_map6:
     case ext_map7:
     case ext_8f09:
--- a/xen/arch/x86/x86_emulate/private.h
+++ b/xen/arch/x86/x86_emulate/private.h
@@ -627,6 +627,7 @@ amd_like(const struct x86_emulate_ctxt *
 #define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16)
 #define vcpu_has_user_msr()    (ctxt->cpuid->feat.user_msr)
 
+#define vcpu_has_amx_fp8()     (ctxt->cpuid->tmul.amx_fp8)
 #define vcpu_has_amx_movrs()   (ctxt->cpuid->tmul.amx_movrs)
 
 #define vcpu_has_avx10(minor)  (ctxt->cpuid->avx10.version >= (minor))
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -7011,7 +7011,7 @@ x86_emulate(
     case X86EMUL_OPC_VEX   (0x0f38, 0x6c): /* tcmmrlfp16ps tmm,tmm,tmm */
     case X86EMUL_OPC_VEX_66(0x0f38, 0x6c): /* tcmmimfp16ps tmm,tmm,tmm */
     {
-        unsigned int vreg = vex.reg ^ 0xf;
+        unsigned int vreg;
 
         if ( ea.type != OP_REG )
             goto unrecognized_insn;
@@ -7024,6 +7024,8 @@ x86_emulate(
             vcpu_must_have(amx_bf16);
         else
             vcpu_must_have(amx_fp16);
+    tmul:
+        vreg = vex.reg ^ 0xf;
         generate_exception_if(modrm_reg == modrm_rm, X86_EXC_UD);
         generate_exception_if(modrm_reg == vreg, X86_EXC_UD);
         generate_exception_if(modrm_rm == vreg, X86_EXC_UD);
@@ -9189,6 +9191,16 @@ x86_emulate(
             avx512_vlen_check(true);
         goto simd_zmm;
 
+    case X86EMUL_OPC_VEX   (5, 0xfd): /* tdpbf8ps tmm,tmm,tmm */
+    case X86EMUL_OPC_VEX_66(5, 0xfd): /* tdphf8ps tmm,tmm,tmm */
+    case X86EMUL_OPC_VEX_F3(5, 0xfd): /* tdphbf8ps tmm,tmm,tmm */
+    case X86EMUL_OPC_VEX_F2(5, 0xfd): /* tdpbhf8ps tmm,tmm,tmm */
+        if ( ea.type != OP_REG )
+            goto unrecognized_insn;
+        generate_exception_if(!mode_64bit() || vex.l || vex.w, X86_EXC_UD);
+        vcpu_must_have(amx_fp8);
+        goto tmul;
+
     case X86EMUL_OPC_EVEX_66(6, 0x4c): /* vrcpph [xyz]mm/mem,[xyz]mm{k} */
     case X86EMUL_OPC_EVEX_66(6, 0x4e): /* vrsqrtph [xyz]mm/mem,[xyz]mm{k} */
         visa_check(_fp16);
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -424,7 +424,7 @@ XEN_CPUFEATURE(AMX__INT8,          21*32
 XEN_CPUFEATURE(AMX__BF16,          21*32+ 1) /*a  AMX-BF16 Instructions */
 XEN_CPUFEATURE(AMX__COMPLEX,       21*32+ 2) /*a  AMX-COMPLEX Instructions */
 XEN_CPUFEATURE(AMX__FP16,          21*32+ 3) /*a  AMX-FP16 Instructions */
-XEN_CPUFEATURE(AMX_FP8,            21*32+ 4) /*   AMX-FP8 Instructions */
+XEN_CPUFEATURE(AMX_FP8,            21*32+ 4) /*a  AMX-FP8 Instructions */
 XEN_CPUFEATURE(AMX_AVX512,         21*32+ 7) /*   AMX-AVX512 Instructions */
 XEN_CPUFEATURE(AMX_MOVRS,          21*32+ 8) /*a  AMX-MOVRS Instructions */