[PATCH v4 20/28] x86emul: support AMX-MOVRS(-only) insns

[Jan Beulich <jbeulich@xxxxxxxx>]

They're direct counterparts of TILELOADD{,T1}, so existing code can
relatively easily be re-used.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
v4: New.

--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -1202,6 +1202,12 @@ static const struct test amx_tile[] = {
     INSN(tilestored,  f3, 0f38, 4b, el, d, no),
 };
 
+static const struct test amx_movrs[] = {
+    /* Element size assumes a 1x1 matrix here. See test_one(). */
+    INSN(tileloaddrs,   f2, 0f38, 4a, el, d, no),
+    INSN(tileloaddrst1, 66, 0f38, 4a, el, d, no),
+};
+
 static const unsigned char vl_all[] = { VL_512, VL_128, VL_256 };
 static const unsigned char vl_128[] = { VL_128 };
 static const unsigned char vl_no128[] = { VL_512, VL_256 };
@@ -1475,7 +1481,7 @@ static void test_one(const struct test *
          * Tile loads/stores require a valid tile configuration. Set up a 1x1
          * tile for %tmm0.
          */
-        if ( test->spc == SPC_0f38 && test->opc == 0x4b )
+        if ( test->spc == SPC_0f38 && (test->opc | 1) == 0x4b )
         {
             static const struct x86_tilecfg tilecfg = {
                 .palette = 1,
@@ -1837,6 +1843,7 @@ void evex_disp8_test(void *instr, struct
     } while ( false )
 
         RUN(adx);
+        RUN(amx_movrs);
         RUN(amx_tile);
         RUN(avx512f);
         RUN(avx512dq);
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -1347,6 +1347,8 @@ static const struct vex {
     { { 0x49, 0x00 }, 2, F, W, pfx_66, W0, L0 }, /* sttilecfg */
     { { 0x49, 0xc0 }, 2, F, N, pfx_no, W0, L0 }, /* tilerelease */
     { { 0x49, 0xc0 }, 2, F, N, pfx_f2, W0, L0 }, /* tilezero */
+    { { 0x4a, VSIB(0) }, 3, F, R, pfx_66, W0, L0 }, /* tileloaddrst1 */
+    { { 0x4a, VSIB(0) }, 3, F, R, pfx_f2, W0, L0 }, /* tileloaddrs */
     { { 0x4b, VSIB(0) }, 3, F, R, pfx_66, W0, L0 }, /* tileloaddt1 */
     { { 0x4b, VSIB(0) }, 3, F, W, pfx_f3, W0, L0 }, /* tilestored */
     { { 0x4b, VSIB(0) }, 3, F, R, pfx_f2, W0, L0 }, /* tileloadd */
@@ -1939,6 +1941,8 @@ static const struct evex {
     { { 0x47 }, 2, T, R, pfx_66, Wn, Ln }, /* vpsllv{d,q} */
     { { 0x49, 0x00 }, 2, F, R, pfx_no, W0, L0 }, /* ldtilecfg */
     { { 0x49, 0x00 }, 2, F, W, pfx_66, W0, L0 }, /* sttilecfg */
+    { { 0x4a, VSIB(0) }, 3, F, R, pfx_66, W0, L0 }, /* tileloaddrst1 */
+    { { 0x4a, VSIB(0) }, 3, F, R, pfx_f2, W0, L0 }, /* tileloaddrs */
     { { 0x4b, VSIB(0) }, 3, F, R, pfx_66, W0, L0 }, /* tileloaddt1 */
     { { 0x4b, VSIB(0) }, 3, F, W, pfx_f3, W0, L0 }, /* tilestored */
     { { 0x4b, VSIB(0) }, 3, F, R, pfx_f2, W0, L0 }, /* tileloadd */
--- a/tools/tests/x86_emulator/x86-emulate.h
+++ b/tools/tests/x86_emulator/x86-emulate.h
@@ -249,6 +249,10 @@ void wrpkru(unsigned int val);
 
 #define cpu_has_xgetbv1             (cpu_has_xsave && 
cpu_policy.xstate.xgetbv1)
 
+#define cpu_has_amx_movrs           (cpu_policy.tmul.amx_movrs && \
+                                     xcr0_mask(X86_XCR0_TILE_CFG | \
+                                               X86_XCR0_TILE_DATA))
+
 #define cpu_has_3dnow_ext            cpu_policy.extd._3dnowext
 #define cpu_has_lzcnt                cpu_policy.extd.abm
 #define cpu_has_sse4a                cpu_policy.extd.sse4a
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -364,7 +364,7 @@ static const struct ext0f38_table {
     [0x44] = { .simd_size = simd_packed_int, .two_op = 1, .d8s = d8s_vl },
     [0x45 ... 0x47] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
     [0x49] = { .simd_size = simd_other, .two_op = 1 },
-    [0x4b] = { .simd_size = simd_other, .two_op = 1, .vsib = 1 },
+    [0x4a ... 0x4b] = { .simd_size = simd_other, .two_op = 1, .vsib = 1 },
     [0x4c] = { .simd_size = simd_packed_fp, .two_op = 1, .d8s = d8s_vl },
     [0x4d] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq },
     [0x4e] = { .simd_size = simd_packed_fp, .two_op = 1, .d8s = d8s_vl },
@@ -1313,6 +1313,8 @@ decode_0f38(struct x86_emulate_state *s,
         break;
 
     case X86EMUL_OPC_EVEX(0, 0x49):    /* ldtilecfg */
+    case X86EMUL_OPC_EVEX_66(0, 0x4a): /* tileloaddrst1 */
+    case X86EMUL_OPC_EVEX_F2(0, 0x4a): /* tileloaddrs */
     case X86EMUL_OPC_EVEX_66(0, 0x4b): /* tileloaddt1 */
     case X86EMUL_OPC_EVEX_F2(0, 0x4b): /* tileloadd */
     case X86EMUL_OPC_EVEX_66(0, 0xe0) ...
--- a/xen/arch/x86/x86_emulate/private.h
+++ b/xen/arch/x86/x86_emulate/private.h
@@ -627,6 +627,8 @@ amd_like(const struct x86_emulate_ctxt *
 #define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16)
 #define vcpu_has_user_msr()    (ctxt->cpuid->feat.user_msr)
 
+#define vcpu_has_amx_movrs()   (ctxt->cpuid->tmul.amx_movrs)
+
 #define vcpu_has_avx10(minor)  (ctxt->cpuid->avx10.version >= (minor))
 #define vcpu_has_avx10_2_aux() (ctxt->cpuid->avx10.avx10_v2_aux)
 
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -6771,6 +6771,16 @@ x86_emulate(
         }
         goto unrecognized_insn;
 
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x4a): /* tileloaddrst1 mem,tmm */
+    case X86EMUL_OPC_EVEX_F2(0x0f38, 0x4a): /* tileloaddrs mem,tmm */
+        generate_exception_if((evex.lr || evex.brs || evex.opmsk || !evex.RX),
+                              X86_EXC_UD);
+        fallthrough;
+    case X86EMUL_OPC_VEX_66(0x0f38, 0x4a): /* tileloaddrst1 mem,tmm */
+    case X86EMUL_OPC_VEX_F2(0x0f38, 0x4a): /* tileloaddrs mem,tmm */
+        vcpu_must_have(amx_movrs);
+        goto tile_load_store;
+
     case X86EMUL_OPC_EVEX_66(0x0f38, 0x4b): /* tileloaddt1 mem,tmm */
     case X86EMUL_OPC_EVEX_F3(0x0f38, 0x4b): /* tilestored tmm,mem */
     case X86EMUL_OPC_EVEX_F2(0x0f38, 0x4b): /* tileloadd mem,tmm */
@@ -6780,6 +6790,7 @@ x86_emulate(
     case X86EMUL_OPC_VEX_66(0x0f38, 0x4b): /* tileloaddt1 mem,tmm */
     case X86EMUL_OPC_VEX_F3(0x0f38, 0x4b): /* tilestored tmm,mem */
     case X86EMUL_OPC_VEX_F2(0x0f38, 0x4b): /* tileloadd mem,tmm */
+    tile_load_store:
     {
         struct x86_tilecfg *cfg = &mmvalp->tilecfg;
         unsigned int row, iter;
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -426,7 +426,7 @@ XEN_CPUFEATURE(AMX__COMPLEX,       21*32
 XEN_CPUFEATURE(AMX__FP16,          21*32+ 3) /*a  AMX-FP16 Instructions */
 XEN_CPUFEATURE(AMX_FP8,            21*32+ 4) /*   AMX-FP8 Instructions */
 XEN_CPUFEATURE(AMX_AVX512,         21*32+ 7) /*   AMX-AVX512 Instructions */
-XEN_CPUFEATURE(AMX_MOVRS,          21*32+ 8) /*   AMX-MOVRS Instructions */
+XEN_CPUFEATURE(AMX_MOVRS,          21*32+ 8) /*a  AMX-MOVRS Instructions */
 
 #endif /* XEN_CPUFEATURE */