[PATCH v4 22/28] x86emul: support AMX-AVX512 insns with GPR operand

[Jan Beulich <jbeulich@xxxxxxxx>]

Since both tile and zmm state are accessed by these insns, this requires
introducing a new enumerator to pass into get_fpu().

As of ISE 056 the APX interaction is unclear; EVEX.V' is supposed to be
set as per the respective exception type, yet the bit needs to be clear
to be able to access eGPR-s. Respective handling is therefore guesswork
for now.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
v4: New.

--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -1948,6 +1948,8 @@ static const struct evex {
     { { 0x49, 0x00 }, 2, F, W, pfx_66, W0, L0 }, /* sttilecfg */
     { { 0x4a, VSIB(0) }, 3, F, R, pfx_66, W0, L0 }, /* tileloaddrst1 */
     { { 0x4a, VSIB(0) }, 3, F, R, pfx_f2, W0, L0 }, /* tileloaddrs */
+    { { 0x4a, 0xc0 }, 2, F, N, pfx_66, W0, L2 }, /* tilemovrow */
+    { { 0x4a, 0xc0 }, 2, F, N, pfx_f3, W0, L2 }, /* tcvtrowd2ps */
     { { 0x4b, VSIB(0) }, 3, F, R, pfx_66, W0, L0 }, /* tileloaddt1 */
     { { 0x4b, VSIB(0) }, 3, F, W, pfx_f3, W0, L0 }, /* tilestored */
     { { 0x4b, VSIB(0) }, 3, F, R, pfx_f2, W0, L0 }, /* tileloadd */
@@ -1982,6 +1984,10 @@ static const struct evex {
     { { 0x66 }, 2, T, R, pfx_66, Wn, Ln }, /* vpblendm{b,w} */
     { { 0x67 }, 2, T, R, pfx_66, W0, Ln }, /* vcvt2ps2phx */
     { { 0x68 }, 2, T, R, pfx_f2, Wn, Ln }, /* vp2intersect{d,q} */
+    { { 0x6d, 0xc0 }, 2, F, N, pfx_no, W0, L2 }, /* tcvtrowps2phh */
+    { { 0x6d, 0xc0 }, 2, F, N, pfx_66, W0, L2 }, /* tcvtrowps2phl */
+    { { 0x6d, 0xc0 }, 2, F, N, pfx_f3, W0, L2 }, /* tcvtrowps2bf16l */
+    { { 0x6d, 0xc0 }, 2, F, N, pfx_f2, W0, L2 }, /* tcvtrowps2bf16h */
     { { 0x70 }, 2, T, R, pfx_66, W1, Ln }, /* vpshldvw */
     { { 0x71 }, 2, T, R, pfx_66, Wn, Ln }, /* vpshldv{d,q} */
     { { 0x72 }, 2, T, R, pfx_66, W1, Ln }, /* vpshrdvw */
--- a/tools/tests/x86_emulator/x86-emulate.c
+++ b/tools/tests/x86_emulator/x86-emulate.c
@@ -247,6 +247,10 @@ int emul_test_get_fpu(
     default:
         return X86EMUL_UNHANDLEABLE;
 
+    case X86EMUL_FPU_zmm_tile:
+        if ( !cpu_has_amx_avx512 )
+            return X86EMUL_UNHANDLEABLE;
+        fallthrough;
     case X86EMUL_FPU_tilecfg:
     case X86EMUL_FPU_tile:
         return cpu_has_amx_tile ? X86EMUL_OKAY : X86EMUL_UNHANDLEABLE;
--- a/tools/tests/x86_emulator/x86-emulate.h
+++ b/tools/tests/x86_emulator/x86-emulate.h
@@ -249,6 +249,9 @@ void wrpkru(unsigned int val);
 
 #define cpu_has_xgetbv1             (cpu_has_xsave && 
cpu_policy.xstate.xgetbv1)
 
+#define cpu_has_amx_avx512          (cpu_policy.tmul.amx_avx512 && \
+                                     xcr0_mask(X86_XCR0_TILE_CFG | \
+                                               X86_XCR0_TILE_DATA))
 #define cpu_has_amx_movrs           (cpu_policy.tmul.amx_movrs && \
                                      xcr0_mask(X86_XCR0_TILE_CFG | \
                                                X86_XCR0_TILE_DATA))
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -384,7 +384,7 @@ static const struct ext0f38_table {
     [0x64 ... 0x66] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
     [0x67] = { .simd_size = simd_other, .d8s = d8s_vl },
     [0x68] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
-    [0x6c] = { .simd_size = simd_other },
+    [0x6c ... 0x6d] = { .simd_size = simd_other },
     [0x70 ... 0x73] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
     [0x74] = { .simd_size = simd_other, .d8s = d8s_vl },
     [0x75 ... 0x76] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
@@ -1312,8 +1312,15 @@ decode_0f38(struct x86_emulate_state *s,
     case X86EMUL_OPC_VEX_F2(0, 0xf7): /* shrx */
         break;
 
+    case X86EMUL_OPC_EVEX_66(0, 0x4a): /* tileloaddrst1 / tilemovrow */
+        if ( s->modrm_mod == 3 )
+        {
+    case X86EMUL_OPC_EVEX_F3(0, 0x4a): /* tcvtrowd2ps */
+            s->desc &= ~Mov;
+            break;
+        }
+        fallthrough;
     case X86EMUL_OPC_EVEX(0, 0x49):    /* ldtilecfg */
-    case X86EMUL_OPC_EVEX_66(0, 0x4a): /* tileloaddrst1 */
     case X86EMUL_OPC_EVEX_F2(0, 0x4a): /* tileloaddrs */
     case X86EMUL_OPC_EVEX_66(0, 0x4b): /* tileloaddt1 */
     case X86EMUL_OPC_EVEX_F2(0, 0x4b): /* tileloadd */
@@ -2101,7 +2108,9 @@ int x86emul_decode(struct x86_emulate_st
             {
                 generate_exception_if(evex_encoded() && !s->evex.u,
                                       X86_EXC_UD);
-                d |= vSIB;
+
+                if ( b != 0x4a || s->modrm_mod != 3 )
+                   d |= vSIB;
             }
             s->simd_size = ext0f38_table[b].simd_size;
             if ( evex_encoded() )
--- a/xen/arch/x86/x86_emulate/private.h
+++ b/xen/arch/x86/x86_emulate/private.h
@@ -628,6 +628,7 @@ amd_like(const struct x86_emulate_ctxt *
 #define vcpu_has_user_msr()    (ctxt->cpuid->feat.user_msr)
 
 #define vcpu_has_amx_fp8()     (ctxt->cpuid->tmul.amx_fp8)
+#define vcpu_has_amx_avx512()  (ctxt->cpuid->tmul.amx_avx512)
 #define vcpu_has_amx_movrs()   (ctxt->cpuid->tmul.amx_movrs)
 
 #define vcpu_has_avx10(minor)  (ctxt->cpuid->avx10.version >= (minor))
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -511,6 +511,12 @@ int x86emul_get_fpu(
 
     switch ( type )
     {
+    case X86EMUL_FPU_zmm_tile:
+        ASSERT(mode_64bit());
+        if ( !(state->xcr0 & X86_XCR0_TILE_CFG) ||
+             !(state->xcr0 & X86_XCR0_TILE_DATA) )
+            return X86EMUL_UNHANDLEABLE;
+        fallthrough;
     case X86EMUL_FPU_zmm:
         if ( !(state->xcr0 & X86_XCR0_ZMM) ||
              !(state->xcr0 & X86_XCR0_HI_ZMM) ||
@@ -572,6 +578,9 @@ int x86emul_get_fpu(
 
         switch ( type )
         {
+        case X86EMUL_FPU_zmm_tile:
+            xcr0_needed = X86_XCR0_TILE_DATA;
+            fallthrough;
         default:
             if ( cr0 & X86_CR0_EM )
             {
@@ -6772,6 +6781,9 @@ x86_emulate(
         goto unrecognized_insn;
 
     case X86EMUL_OPC_EVEX_66(0x0f38, 0x4a): /* tileloaddrst1 mem,tmm */
+        if ( ea.type != OP_MEM )
+            goto tilemovrow;
+        fallthrough;
     case X86EMUL_OPC_EVEX_F2(0x0f38, 0x4a): /* tileloaddrs mem,tmm */
         generate_exception_if((evex.lr || evex.brs || evex.opmsk || !evex.RX),
                               X86_EXC_UD);
@@ -6951,6 +6963,49 @@ x86_emulate(
         generate_exception_if(vex.w, X86_EXC_UD);
         goto simd_0f_avx2;
 
+    tilemovrow:                             /* tilemovrow r32,tmm,zmm */
+    case X86EMUL_OPC_EVEX_F3(0x0f38, 0x4a): /* tcvtrowd2ps r32,tmm,zmm */
+    case X86EMUL_OPC_EVEX   (0x0f38, 0x6d): /* tcvtrowps2phh r32,tmm,zmm */
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x6d): /* tcvtrowps2phl r32,tmm,zmm */
+    case X86EMUL_OPC_EVEX_F3(0x0f38, 0x6d): /* tcvtrowps2bf16l r32,tmm,zmm */
+    case X86EMUL_OPC_EVEX_F2(0x0f38, 0x6d): /* tcvtrowps2bf16h r32,tmm,zmm */
+        if ( ea.type != OP_REG )
+            goto unrecognized_insn;
+        vcpu_must_have(amx_avx512);
+        generate_exception_if((evex.w || evex.brs || evex.opmsk ||
+                               evex.lr != 2 ||
+                               (!evex.RX && !(state->xcr0 & X86_XCR0_APX))),
+                              X86_EXC_UD);
+
+        get_fpu(X86EMUL_FPU_zmm_tile);
+        sttilecfg(&mmvalp->tilecfg);
+
+        generate_exception_if(!tile_valid(modrm_rm, &mmvalp->tilecfg,
+                                          PALETTE(AMX)),
+                              X86_EXC_UD);
+        generate_exception_if(mmvalp->tilecfg.colsb[modrm_rm] & 3,
+                              X86_EXC_UD);
+
+        ea.reg = decode_evex_gpr(evex.reg | (evex.RX << 4), &_regs,
+                                 &state->egpr, ctxt);
+
+        opc = init_evex(stub);
+        opc[0] = b;
+        /* Convert GPR source to %eax. */
+        evex.reg = 0xf;
+        evex.RX = 1;
+        opc[1] = modrm;
+        insn_bytes = EVEX_PFX_BYTES + 2;
+        place_ret(&opc[2]);
+
+        copy_EVEX(opc, evex);
+        invoke_stub("", "", "=g" (dummy) : "a" (*ea.reg));
+
+        put_stub(stub);
+        state->simd_size = simd_none;
+        dst.type = OP_NONE;
+        break;
+
     case X86EMUL_OPC_EVEX_66(0x0f38, 0x4d): /* vrcp14s{s,d} xmm/mem,xmm,xmm{k} 
*/
     case X86EMUL_OPC_EVEX_66(0x0f38, 0x4f): /* vrsqrt14s{s,d} 
xmm/mem,xmm,xmm{k} */
         visa_check(f);
--- a/xen/arch/x86/x86_emulate/x86_emulate.h
+++ b/xen/arch/x86/x86_emulate/x86_emulate.h
@@ -87,6 +87,7 @@ enum x86_emulate_fpu_type {
     X86EMUL_FPU_zmm, /* AVX512 instruction set (%zmm0-%zmm7/31) */
     X86EMUL_FPU_tilecfg, /* AMX configuration (tilecfg) */
     X86EMUL_FPU_tile, /* AMX instruction set (%tmm0-%tmmN) */
+    X86EMUL_FPU_zmm_tile, /* AMX and AVX512/AVX10 instruction sets */
     /* This sentinel will never be passed to ->get_fpu(). */
     X86EMUL_FPU_none
 };