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xen-devel
RE: [Xen-devel] [PATCH] X86: cpuid faulting feature enable
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To: |
"Liu, Jinsong" <jinsong.liu@xxxxxxxxx>, Keir Fraser <keir.xen@xxxxxxxxx>, Jan Beulich <JBeulich@xxxxxxxxxx> |
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Subject: |
RE: [Xen-devel] [PATCH] X86: cpuid faulting feature enable |
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From: |
"Liu, Jinsong" <jinsong.liu@xxxxxxxxx> |
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Date: |
Sat, 2 Jul 2011 02:14:24 +0800 |
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Cc: |
"Tian, Kevin" <kevin.tian@xxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxx>, "Shan, Haitao" <haitao.shan@xxxxxxxxx>, "Li, Xin" <xin.li@xxxxxxxxx> |
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Fri, 01 Jul 2011 11:15:04 -0700 |
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Thread-topic: |
[Xen-devel] [PATCH] X86: cpuid faulting feature enable |
Liu, Jinsong wrote:
> Keir Fraser wrote:
>> On 01/07/2011 18:48, "Liu, Jinsong" <jinsong.liu@xxxxxxxxx> wrote:
>>
>>>> Down to a particular stepping? That surely doesn't make sense for
>>>> anything but your own experimenting.
>>>
>>> Yes, it's some ugly.
>>> Currently cpuid faulting is not a architecturally commited feature,
>>> and, some other Intel processors (which do not has cpuid faulting
>>> feature) also has 0xceh MSR. Hence I use current way for safe.
>>> However, I marked it as FIXME to update in the future accordingly.
>>
>> But Intel's own supporting document states that bit 31 of the
>> PLATFORM_INFO MSR should be sufficient to identify the cpuid faulting
>> feature. Do you really need the stepping check as well? Could you
>> just do a rdmsr_safe read-and-check of PLATFORM_INFO_MSR[31] instead?
>>
>> It would be okay for other Intel CPUs to have MSR 0xce, so long as
>> they don't set bit 31...
>>
>> -- Keir
>
> That's good. It does formally state.
> We can move family/model/stepping now.
sorry, remove. my poor english :(
>
> Thanks,
> Jinsong
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