RE: [Xen-devel] [PATCH] x86/hvm: accelerate I/O intercept handling

["Cui, Dexuan" <dexuan.cui@xxxxxxxxx>]

Actually in 15425:6e934c799051, VMX  once enabled the feature, but IIRC, later 
Keir removed that in some cleanup patches and let the 
EXIT_REASON_IO_INSTRUCTION handler invoke handle_mmio() also -- I don't 
remember how people commented the slowness of IN/OUT emulation caused the 
change...

One thing is: IIRC, old Intel CPUs don't supply the info, but your patch 
doesn't check that... so your patch can break the CPUs. Please refer to 15425.

Thanks,
--- Dexuan

-----Original Message-----
From: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx 
[mailto:xen-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf Of Andre Przywara
Sent: 2010年3月31日 16:48
To: Keir Fraser; xen-devel
Subject: [Xen-devel] [PATCH] x86/hvm: accelerate I/O intercept handling

Hi,

currently we go through the emulator every time a HVM guest does an I/O 
port access (in/out). This is unnecessary most of the times, as both VMX 
and SVM provide all the necessary information already in the VMCS/VMCB. 
String instructions are not covered by this shortcut, but they are quite 
rare and we would need to access the guest memory anyway.
This patch decodes the information from VMCB/VMCS and calls a simple 
handle_mmio wrapper. In handle_mmio() itself the emulation part will 
simply be skipped, this approach avoids code duplication.
Since the vendor specific part is quite trivial, I implemented both the 
VMX and SVM part, please check the VMX part for sanity.

I boot-tested both versions and ran some simple benchmarks.
A micro benchmark (hammering an I/O port in a tight loop) shows a 
significant performance improvement (down to 66% of the time needed to 
handle the intercept on an AMD K8, measured in the guest with TSC).
Even with reading a 1GB file from an emulated IDE harddisk (Dom0 cached) 
I could get a  4-5% improvement.
Some guest code (e.g. the TCP stack in some Windows version) exercises 
the PM-Timer I/O port (0x1F48) very often (multiple 10,000 times per 
second), these workloads also benefit with up to 5% improvement from 
this patch.

Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>

Regards,
Andre.

-- 
Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany
Tel: +49 351 448-3567-12

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