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Re: [Xen-devel] TPR write optimization (even improves 2003 sp2)

To: James Harper <james.harper@xxxxxxxxxxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: Re: [Xen-devel] TPR write optimization (even improves 2003 sp2)
From: Keir Fraser <keir.fraser@xxxxxxxxxxxxx>
Date: Wed, 07 Jan 2009 10:26:02 +0000
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On 07/01/2009 10:05, "James Harper" <james.harper@xxxxxxxxxxxxxxxx> wrote:

>> Sometimes it triggers an interrupt to be delivered. So you'd need a
> TPR
>> threshold too to cause a VMEXIT sometimes. Or perhaps map the whole
> APIC
>> page and work it out yourself (possibly the Citrix drivers do this,
> but
>> I'm not really familiar with them).
> 
> I can't see anything that would trigger an interrupt beyond
> vlapic_write(). Is it just the act of invoking a VMEXIT that triggers
> the interrupt delivery?

Yes. See vmx_intr_assist().

> From memory, there is a register somewhere that says what the highest
> interrupt level that is currently blocked is... I'll look at that. This
> doesn't actually sound that hard...

An interrupt is delivered if:
  highest_prio(IRR) > max(highest_prio(ISR), TPR).

Where highest_prio() is based on a backwards bitmap scan.

If you go down the route of setting a TPR threshold for vmexit, that would
be (hp = highest_prio):
  TPR_thresh = ((hp(IRR) > hp(ISR)) && (hp(IRR) < TPR)) ? hp(IRR) : 0

Where VMEXIT occurs if TPR is updated to a value less than the threshold.

 -- Keir



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