WARNING - OLD ARCHIVES

This is an archived copy of the Xen.org mailing list, which we have preserved to ensure that existing links to archives are not broken. The live archive, which contains the latest emails, can be found at http://lists.xen.org/
   
 
 
Xen 
 
Home Products Support Community News
 
   
 

xen-devel

[Xen-devel] Re: [PATCH] [RFC] More fp instructions for realmode emulatio

To: Andi Kleen <andi@xxxxxxxxxxxxxx>
Subject: [Xen-devel] Re: [PATCH] [RFC] More fp instructions for realmode emulation (Enables booting OS/2 as a HVM guest on Intel/VT hardware)
From: Keir Fraser <keir.fraser@xxxxxxxxxxxxx>
Date: Mon, 03 Mar 2008 17:30:13 +0000
Cc: xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxx>, Trolle Selander <trolle.selander@xxxxxxxxx>
Delivery-date: Mon, 03 Mar 2008 09:38:08 -0800
Envelope-to: www-data@xxxxxxxxxxxxxxxxxx
In-reply-to: <20080303165929.GC9853@xxxxxxxxxxxxxxxxxx>
List-help: <mailto:xen-devel-request@lists.xensource.com?subject=help>
List-id: Xen developer discussion <xen-devel.lists.xensource.com>
List-post: <mailto:xen-devel@lists.xensource.com>
List-subscribe: <http://lists.xensource.com/cgi-bin/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=subscribe>
List-unsubscribe: <http://lists.xensource.com/cgi-bin/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=unsubscribe>
Sender: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
Thread-index: Ach9VDzAew0lLOlHEdyK1AAX8io7RQ==
Thread-topic: [PATCH] [RFC] More fp instructions for realmode emulation (Enables booting OS/2 as a HVM guest on Intel/VT hardware)
User-agent: Microsoft-Entourage/11.3.6.070618
On 3/3/08 16:59, "Andi Kleen" <andi@xxxxxxxxxxxxxx> wrote:

>>> Yes you definitely need to. That was a kernel crash bug on native Linux
>>> some time ago...
>>> 
>>> Also you need to do the same for any FXSAVEs/FXRSTORs if you haven't
>>> already.
>> 
>> FXSAVE/FXRSTOR do not flush pending FPU exceptions, right?
> 
> Yes they do not, but there are other ways to make them #GP

We don't trust FXRSTOR but we do trust FXSAVE. The AMD manual says that
FXRSTOR will #GP if 1s are written to MXCSR reserved bits, but I take this
to be a cut-and-paste typo since FXSAVE does not write to MXCSR.

If there's real evidence of FXSAVE causing #GP dependent on current FPU
state, I'd be very happy to find out about it!

 -- Keir



_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-devel

<Prev in Thread] Current Thread [Next in Thread>