RE: [Xen-devel] [PATCH][VT]vga acceleration for cirrus logic device model

["Jiang, Yunhong" <yunhong.jiang@xxxxxxxxx>]

Keir Fraser wrote:

> Depends what the 1:1 page table is used for (it's also supposed to be
> the phys-to-machine table, isn't it?). If we ignore that latter use (I
> think it can be worked out later) then we are okay so long as the
> guest can never run in 64-bit mode with paging disabled. IIRC that is
> not a valid execution mode?

I think 1:1 page table is used for both paging disabled running AND
physical-to-machine table, so agree that if we ignore the
physical-to-machine table, it is ok with current 1:1 page table
implementaion, but just as you said, we need work out later for
phys-to-machine mapping.

Thanks
Yunhong Jiang
> 
> If it can only run with paging disabled in 16- or 32-bit mode, it
> can't access above 4G pseudophys anyway. :-)
> 
>   -- Keir


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