Re: [Xen-devel] [PATCH][VT]vga acceleration for cirrus logic device model

[Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>]

On 23 Sep 2005, at 13:51, Jiang, Yunhong wrote:

> There may be some problem on current 1:1 page table for 64 bit guest.
> Considering a guest has memory more than 4G. Current implementation may
> cause problem on physical to machine mapping.
>
> However, this patch works on currently 1:1 page table implementation. 
> So
> how about check it in firstly, and I will provide a total solution to
> improve the whole thing, because I think the 4 level 1:1 page table is
> more complex than 3 level, we may have to provide dynamical setting,
> still on consideration.
Depends what the 1:1 page table is used for (it's also supposed to be 
the phys-to-machine table, isn't it?). If we ignore that latter use (I 
think it can be worked out later) then we are okay so long as the guest 
can never run in 64-bit mode with paging disabled. IIRC that is not a 
valid execution mode?
If it can only run with paging disabled in 16- or 32-bit mode, it can't 
access above 4G pseudophys anyway. :-)
 -- Keir


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