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Re: [Xen-devel] [PATCH] Fixing ioapic write order in io_apic_write_remap

To: "Weidong Han" <weidong.han@xxxxxxxxx>
Subject: Re: [Xen-devel] [PATCH] Fixing ioapic write order in io_apic_write_remap_rte
From: "Jan Beulich" <JBeulich@xxxxxxxxxx>
Date: Mon, 09 Aug 2010 09:26:09 +0100
Cc: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxx>, Yunhong Jiang <yunhong.jiang@xxxxxxxxx>, Allen M Kay <allen.m.kay@xxxxxxxxx>, Keir Fraser <keir.fraser@xxxxxxxxxxxxx>
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>>> On 09.08.10 at 05:18, "Han, Weidong" <weidong.han@xxxxxxxxx> wrote:
> At the end of io_apic_write_remap_rte, it writes new entry (remapped 
> interrupt) to ioapic. But it writes low 32 bits before high 32 bits, it 
> unmasks interrupt before writing high 32 bits if 'mask' bit in low 32 bits is 
> cleared. Thus it may result in issues. This patch fixes this issue by writing 
> high 32 bits before low 32 bits. 

While I fully agree with this change, isn't there another problem in the
error handling path in that the mask bit would not get cleared again
if the write is to the upper half of the RTE?


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