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[Xen-devel] [PATCH] Fixing ioapic write order in io_apic_write_remap_rte

To: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: [Xen-devel] [PATCH] Fixing ioapic write order in io_apic_write_remap_rte
From: "Han, Weidong" <weidong.han@xxxxxxxxx>
Date: Mon, 9 Aug 2010 11:18:01 +0800
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Cc: "Jiang, Yunhong" <yunhong.jiang@xxxxxxxxx>, "Kay, Allen M" <allen.m.kay@xxxxxxxxx>, Keir Fraser <keir.fraser@xxxxxxxxxxxxx>
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Thread-topic: [Xen-devel] [PATCH] Fixing ioapic write order in io_apic_write_remap_rte
At the end of io_apic_write_remap_rte, it writes new entry (remapped interrupt) 
to ioapic. But it writes low 32 bits before high 32 bits, it unmasks interrupt 
before writing high 32 bits if 'mask' bit in low 32 bits is cleared. Thus it 
may result in issues. This patch fixes this issue by writing high 32 bits 
before low 32 bits. 

Signed-off-by: Jiang, Yunhong <yunhong.jiang@xxxxxxxxx>
Signed-off-by: Weidong Han <weidong.han@xxxxxxxxx>

diff -r 6c18aa5a848e xen/drivers/passthrough/vtd/intremap.c
--- a/xen/drivers/passthrough/vtd/intremap.c    Mon Aug 02 12:49:12 2010 -0400
+++ b/xen/drivers/passthrough/vtd/intremap.c    Fri Aug 06 11:47:03 2010 -0400
@@ -444,10 +444,10 @@ void io_apic_write_remap_rte(
     /* write new entry to ioapic */
+    *IO_APIC_BASE(apic) = reg + 1;
+    *(IO_APIC_BASE(apic)+4) = *(((u32 *)&old_rte)+1);
     *IO_APIC_BASE(apic) = reg;
     *(IO_APIC_BASE(apic)+4) = *(((u32 *)&old_rte)+0);
-    *IO_APIC_BASE(apic) = reg + 1;
-    *(IO_APIC_BASE(apic)+4) = *(((u32 *)&old_rte)+1);
 #if defined(__i386__) || defined(__x86_64__)

Attachment: fix-IR-write.patch
Description: fix-IR-write.patch

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