Re: [Xen-devel] RE: [PATCH]xend: fix a typo in pci.py

[Kouya Shimura <kouya@xxxxxxxxxxxxxx>]

Cui, Dexuan writes:
> 2) When performing reset, we should sleep at least 100ms; in current code, 
> it's incorrect somewhere we sleep 0.2s and somewhere 0.01s.

As long as I read "PCI Bus Power Management Interface Spec Rev 1.2",
the state transition recovery time across D3hot/D0 is 10ms.
Is it really neeeded to sleep 100ms?
In the case of FLR, 100ms should be necessary.

Thanks,
Kouya

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