[PATCH v4 12/28] x86/HVM: respect AMX tile dimensions for emulation caching

[Jan Beulich <jbeulich@xxxxxxxx>]

Both caches may need higher capacity, and the upper bound needs to be
determined dynamically based on CPUID policy (for AMX'es TILELOAD /
TILESTORE at least). For now we need to use the maximum policy there,
until vCPU creation happens after CPUID setup.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
v4: New.
---
TBD: With hvmemul_cache_init() now becoming CPUID policy dependent, we
     could of course take the opportunity and also reduce overhead when
     AVX512 (and maybe even AVX) is unavailable (in the future: to the
     guest); AVX10/256 may in particular become of interest here.

--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -20,6 +20,7 @@
 #include <xen/xvmalloc.h>
 
 #include <asm/altp2m.h>
+#include <asm/cpu-policy.h>
 #include <asm/event.h>
 #include <asm/i387.h>
 #include <asm/xstate.h>
@@ -3064,9 +3065,34 @@ int hvmemul_cache_init(struct vcpu *v)
      */
     unsigned int nents = 16 * 2 * (CONFIG_PAGING_LEVELS + 1);
     unsigned int i, max_bytes = 64;
+    /*
+     * NB: Want to use guest policy here, once that gets established ahead
+     * of vCPU creation.
+     */
+    const struct cpu_policy *p = &hvm_max_cpu_policy;
     struct hvmemul_cache *cache;
 
     /*
+     * AMX load/store insns can access up to max_rows independent linear
+     * addresses, up to bytes_per_row in size. Each such linear range can
+     * again span a page boundary.
+     */
+    if ( p->tile.max_palette >= 1 )
+    {
+        unsigned int tents = (p->tile.palette1.bytes_per_row /
+                              sizeof(cache->ents->data)) + 1;
+
+        tents = (tents + 2 * CONFIG_PAGING_LEVELS) *
+                p->tile.palette1.max_rows;
+
+        if ( tents > nents )
+            nents = tents;
+
+        if ( p->tile.palette1.bytes_per_row > max_bytes )
+            max_bytes = p->tile.palette1.bytes_per_row;
+    }
+
+    /*
      * Account for each insn byte individually, both for simplicity and to
      * leave some slack space.
      */