Replace all sensitive instructions in dual compile IVT.s.
Now the total change against upstream is:
89 files changed, 8857 insertions(+), 1059 deletions(-)
All in one patch file size is 11643 lines.
If we can seperate those common file movement from arch/x86/xen
to driver/xen, additional 1.2-1.4K lines can be saved.
Thanks, eddie
Signed-off-by: Yaozu (Eddie) Dong <eddie.dong@xxxxxxxxx>
diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S
index f2306ae..d516bf4 100644
--- a/arch/ia64/kernel/ivt.S
+++ b/arch/ia64/kernel/ivt.S
@@ -19,6 +19,7 @@
* Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
* VA Linux Systems Japan K.K.
* pv_ops.
+ * Yaozu (Eddie) Dong <eddie.dong@xxxxxxxxx>
*/
/*
* This file defines the interruption vector table used by the CPU.
@@ -338,7 +339,7 @@ ENTRY(alt_itlb_miss)
DBG_FAULT(3)
MOV_FROM_IFA(r16) // get address that caused the TLB miss
movl r17=PAGE_KERNEL
- MOV_FROM_IPSR(r21)
+ MOV_FROM_IPSR(p0,r21)
movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
mov r31=pr
;;
@@ -378,7 +379,7 @@ ENTRY(alt_dtlb_miss)
movl r17=PAGE_KERNEL
MOV_FROM_ISR(r20)
movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
- MOV_FROM_IPSR(r21)
+ MOV_FROM_IPSR(p0,r21)
mov r31=pr
mov r24=PERCPU_ADDR
;;
@@ -417,7 +418,7 @@ ENTRY(alt_dtlb_miss)
dep r21=-1,r21,IA64_PSR_ED_BIT,1
;;
or r19=r19,r17 // insert PTE control bits into r19
-(p6) mov cr.ipsr=r21
+ MOV_FROM_IPSR(p6,r21)
;;
ITC_D(p7, r19, r18) // insert the TLB entry
mov pr=r31,-1
@@ -618,9 +619,9 @@ ENTRY(iaccess_bit)
/*
* Erratum 10 (IFA may contain incorrect address) has "NoFix"
status.
*/
- mov r17=cr.ipsr
+ MOV_FROM_IPSR(p0,r17)
;;
- mov r18=cr.iip
+ MOV_FROM_IIP(r18)
tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
;;
(p6) mov r16=r18 // if so, use cr.iip
instead of cr.ifa
@@ -745,7 +746,7 @@ ENTRY(break_fault)
*/
DBG_FAULT(11)
mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current
task (12 cyc)
- MOV_FROM_IPSR(r29) // M2 (12 cyc)
+ MOV_FROM_IPSR(p0,r29) // M2 (12 cyc)
mov r31=pr // I0 (2 cyc)
MOV_FROM_IIM(r17) // M2 (2 cyc)
@@ -1057,11 +1058,11 @@ ENTRY(dispatch_illegal_op_fault)
.prologue
.body
SAVE_MIN_WITH_COVER
- ssm psr.ic | PSR_DEFAULT_BITS
+ SSM_PSR_IC_AND_DEFAULT_BITS(r3,r24)
;;
srlz.i // guarantee that interruption collection is on
;;
-(p15) ssm psr.i // restore psr.i
+ SSM_PSR_I(p15,r3) // restore psr.i
adds r3=8,r2 // set up second base pointer for SAVE_REST
;;
alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
@@ -1109,15 +1110,15 @@ ENTRY(non_syscall)
// suitable spot...
alloc r14=ar.pfs,0,0,2,0
- mov out0=cr.iim
+ MOV_FROM_IIM(out0)
add out1=16,sp
adds r3=8,r2 // set up second base pointer
for SAVE_REST
- ssm psr.ic | PSR_DEFAULT_BITS
+ SSM_PSR_IC_AND_DEFAULT_BITS(r15,r24)
;;
srlz.i // guarantee that interruption
collection is on
;;
-(p15) ssm psr.i // restore psr.i
+ SSM_PSR_I(p15,r15) // restore psr.i
movl r15=ia64_leave_kernel
;;
SAVE_REST
@@ -1143,14 +1144,14 @@ ENTRY(dispatch_unaligned_handler)
SAVE_MIN_WITH_COVER
;;
alloc r14=ar.pfs,0,0,2,0 // now it's safe (must
be first in insn group!)
- mov out0=cr.ifa
+ MOV_FROM_IFA(out0)
adds out1=16,sp
- ssm psr.ic | PSR_DEFAULT_BITS
+ SSM_PSR_IC_AND_DEFAULT_BITS(r3,r24)
;;
srlz.i // guarantee that
interruption collection is on
;;
-(p15) ssm psr.i // restore psr.i
+ SSM_PSR_I(p15,r3) // restore psr.i
adds r3=8,r2 // set up second base
pointer
;;
SAVE_REST
@@ -1182,17 +1183,17 @@ ENTRY(dispatch_to_fault_handler)
*/
SAVE_MIN_WITH_COVER_R19
alloc r14=ar.pfs,0,0,5,0
- mov out0=r15
MOV_FROM_ISR(out1)
MOV_FROM_IFA(out2)
MOV_FROM_IIM(out3)
MOV_FROM_ITIR(out4)
;;
- ssm psr.ic | PSR_DEFAULT_BITS
+ SSM_PSR_IC_AND_DEFAULT_BITS(r3, out0)
+ mov out0=r15
;;
srlz.i // guarantee that
interruption collection is on
;;
-(p15) ssm psr.i // restore psr.i
+ SSM_PSR_I(p15,r3) // restore psr.i
adds r3=8,r2 // set up second base
pointer for SAVE_REST
;;
SAVE_REST
@@ -1211,8 +1212,8 @@ END(dispatch_to_fault_handler)
// 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
ENTRY(page_not_present)
DBG_FAULT(20)
- mov r16=cr.ifa
- rsm psr.dt
+ MOV_FROM_IFA(r16)
+ RSM_PSR_DT
/*
* The Linux page fault handler doesn't expect non-present pages
to be in
* the TLB. Flush the existing entry now, so we meet that
expectation.
@@ -1231,8 +1232,8 @@ END(page_not_present)
// 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
ENTRY(key_permission)
DBG_FAULT(21)
- mov r16=cr.ifa
- rsm psr.dt
+ MOV_FROM_IFA(r16)
+ RSM_PSR_DT
mov r31=pr
;;
srlz.d
@@ -1244,8 +1245,8 @@ END(key_permission)
// 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
ENTRY(iaccess_rights)
DBG_FAULT(22)
- mov r16=cr.ifa
- rsm psr.dt
+ MOV_FROM_IFA(r16)
+ RSM_PSR_DT
mov r31=pr
;;
srlz.d
@@ -1270,7 +1271,7 @@ END(daccess_rights)
// 0x5400 Entry 24 (size 16 bundles) General Exception
(5,32,34,36,38,39)
ENTRY(general_exception)
DBG_FAULT(24)
- mov r16=cr.isr
+ MOV_FROM_ISR(r16)
mov r31=pr
;;
cmp4.eq p6,p0=0,r16
@@ -1299,8 +1300,8 @@ END(disabled_fp_reg)
ENTRY(nat_consumption)
DBG_FAULT(26)
- mov r16=cr.ipsr
- mov r17=cr.isr
+ MOV_FROM_IPSR(p0,r16);
+ MOV_FROM_ISR(r17);
mov r31=pr // save PR
;;
and r18=0xf,r17 // r18 =
cr.ipsr.code{3:0}
@@ -1310,10 +1311,10 @@ ENTRY(nat_consumption)
dep r16=-1,r16,IA64_PSR_ED_BIT,1
(p6) br.cond.spnt 1f // branch if (cr.ispr.na == 0 ||
cr.ipsr.code{3:0} != LFETCH)
;;
- mov cr.ipsr=r16 // set cr.ipsr.na
+ MOV_TO_IPSR(r16,r18);
mov pr=r31,-1
;;
- rfi
+ RFI
1: mov pr=r31,-1
;;
@@ -1335,23 +1336,23 @@ ENTRY(speculation_vector)
*
* cr.imm contains zero_ext(imm21)
*/
- mov r18=cr.iim
+ MOV_FROM_IIM(r18)
;;
- mov r17=cr.iip
+ MOV_FROM_IIP(r17)
shl r18=r18,43 // put sign bit in position
(43=64-21)
;;
- mov r16=cr.ipsr
+ MOV_FROM_IPSR(p0,r16)
shr r18=r18,39 // sign extend (39=43-4)
;;
add r17=r17,r18 // now add the offset
;;
- mov cr.iip=r17
+ MOV_FROM_IIP(r17)
dep r16=0,r16,41,2 // clear EI
;;
- mov cr.ipsr=r16
+ MOV_FROM_IPSR(p0,r16)
;;
RFI
@@ -1492,11 +1493,11 @@ ENTRY(ia32_intercept)
DBG_FAULT(46)
#ifdef CONFIG_IA32_SUPPORT
mov r31=pr
- mov r16=cr.isr
+ MOV_FROM_ISR(r16)
;;
extr.u r17=r16,16,8 // get ISR.code
mov r18=ar.eflag
- mov r19=cr.iim // old eflag value
+ MOV_FROM_IIM(r19) // old eflag value
;;
cmp.ne p6,p0=2,r17
(p6) br.cond.spnt 1f // not a system flag fault
@@ -1662,12 +1663,12 @@ END(ia32_interrupt)
ENTRY(dispatch_to_ia32_handler)
SAVE_MIN
;;
- mov r14=cr.isr
- ssm psr.ic | PSR_DEFAULT_BITS
+ MOV_FROM_ISR(r14)
+ SSM_PSR_IC_AND_DEFAULT_BITS(r3,r24)
;;
srlz.i // guarantee that
interruption collection is on
;;
-(p15) ssm psr.i
+ SSM_PSR_I(p15,r3)
adds r3=8,r2 // Base pointer for SAVE_REST
;;
SAVE_REST
diff --git a/arch/ia64/kernel/minstate.h b/arch/ia64/kernel/minstate.h
index 9e18fb0..b17670b 100644
--- a/arch/ia64/kernel/minstate.h
+++ b/arch/ia64/kernel/minstate.h
@@ -35,7 +35,7 @@
mov r27=ar.rsc; /* M */
\
mov r20=r1; /* A */
\
mov r25=ar.unat; /* M */
\
- MOV_FROM_IPSR(r29); /* M */
\
+ MOV_FROM_IPSR(p0,r29); /* M */
\
mov r26=ar.pfs; /* I */
\
MOV_FROM_IIP(r28); /* M */
\
mov r21=ar.fpsr; /* M */
\
diff --git a/arch/ia64/xen/xenivt.S b/arch/ia64/xen/xenivt.S
diff --git a/include/asm-ia64/native/inst.h
b/include/asm-ia64/native/inst.h
index 7e91396..a7d3689 100644
--- a/include/asm-ia64/native/inst.h
+++ b/include/asm-ia64/native/inst.h
@@ -47,8 +47,8 @@
#define MOV_FROM_IHA(reg) \
mov reg = cr.iha
-#define MOV_FROM_IPSR(reg) \
- mov reg = cr.ipsr
+#define MOV_FROM_IPSR(pred,reg) \
+(pred) mov reg = cr.ipsr
#define MOV_FROM_IIM(reg) \
mov reg = cr.iim
diff --git a/include/asm-ia64/xen/inst.h b/include/asm-ia64/xen/inst.h
index 1e92d02..250f21a 100644
--- a/include/asm-ia64/xen/inst.h
+++ b/include/asm-ia64/xen/inst.h
@@ -49,10 +49,10 @@
;; \
ld8 reg = [reg]
-#define MOV_FROM_IPSR(reg) \
- movl reg = XSI_IPSR; \
+#define MOV_FROM_IPSR(pred,reg) \
+(pred) movl reg = XSI_IPSR; \
;; \
- ld8 reg = [reg]
+(pred) ld8 reg = [reg]
#define MOV_FROM_IIM(reg) \
movl reg = XSI_IIM; \
diff --git a/include/asm-ia64/xen/minstate.h
b/include/asm-ia64/xen/minstate.h
index 7cdebc2..7439300 100644
--- a/include/asm-ia64/xen/minstate.h
+++ b/include/asm-ia64/xen/minstate.h
@@ -30,7 +30,7 @@
mov r27=ar.rsc; /* M */
\
mov r20=r1; /* A */
\
mov r25=ar.unat; /* M */
\
- MOV_FROM_IPSR(r29); /* M */
\
+ MOV_FROM_IPSR(p0,r29); /* M */
\
MOV_FROM_IIP(r28); /* M */
\
mov r21=ar.fpsr; /* M */
\
mov r26=ar.pfs; /* I */
\
ivt_sensitive5.patch
Description: ivt_sensitive5.patch
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