Re: [Xen-devel] AMD IOMMU intremap tables and IOAPICs

[Tim Deegan <tim@xxxxxxx>]

At 16:54 +0100 on 06 Sep (1315328056), Andrew Cooper wrote:
> On 06/09/11 16:47, George Dunlap wrote:
> > Wei,
> >
> > Quick question:  Am I reading the code correctly, that even with
> > per-device interrupt remap tables, that GSIs are accounted to the
> > intremap table of the corresponding IOAPIC, presumably because the
> > IOMMU sees interrupts generated as GSIs as coming from the IOAPIC?  In
> > that case, then we need all devices sharing the same IOAPIC must not
> > have any vector collisions.  Is that correct?
> 
> Based on the ICH10 IO-APIC documentation with respect to auto EOIs, we
> cant have any two IRQs across any IO-APICs sharing a vector,
> irrespective of IOMMU or not.  (Because the EOI'ing an IO-APIC entry
> only takes account of vector and not destination)

If this is the case, is there any point in having per-CPU IDTs?  
Or per-device remapping tables?

Tim.

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