[Xen-devel] Re: [PATCH 05/10] x86/PCI: Clean up pci_cache_line_size

[Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>]

On Tue, 12 May 2009 14:48:06 -0700
Jeremy Fitzhardinge <jeremy@xxxxxxxx> wrote:

> From: Alex Nixon <alex.nixon@xxxxxxxxxx>
> 
> Separate out x86 cache_line_size initialisation code into its own
> function (so it can be shared by Xen later in this patch series)
> 
> [Impact: cleanup]
> Signed-off-by: Alex Nixon <alex.nixon@xxxxxxxxxx>
> Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@xxxxxxxxxx>
> Reviewed-by: "H. Peter Anvin" <hpa@xxxxxxxxx>
> Reviewed-by: Matthew Wilcox <willy@xxxxxxxxxxxxxxx>
> ---
>  arch/x86/include/asm/pci_x86.h |    1 +
>  arch/x86/pci/common.c          |   17 +++++++++++------
>  2 files changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/x86/include/asm/pci_x86.h
> b/arch/x86/include/asm/pci_x86.h index e60fd3e..5401ca2 100644
> --- a/arch/x86/include/asm/pci_x86.h
> +++ b/arch/x86/include/asm/pci_x86.h
> @@ -45,6 +45,7 @@ enum pci_bf_sort_state {
>  extern unsigned int pcibios_max_latency;
>  
>  void pcibios_resource_survey(void);
> +void pcibios_set_cache_line_size(void);
>  
>  /* pci-pc.c */
>  
> diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
> index 2202b62..011ff45 100644
> --- a/arch/x86/pci/common.c
> +++ b/arch/x86/pci/common.c
> @@ -412,26 +412,31 @@ struct pci_bus * __devinit
> pcibios_scan_root(int busnum) 
>  extern u8 pci_cache_line_size;
>  
> -int __init pcibios_init(void)
> +void __init pcibios_set_cache_line_size(void)
>  {
>       struct cpuinfo_x86 *c = &boot_cpu_data;
>  
> -     if (!raw_pci_ops) {
> -             printk(KERN_WARNING "PCI: System does not support
> PCI\n");
> -             return 0;
> -     }
> -
>       /*
>        * Assume PCI cacheline size of 32 bytes for all x86s except
> K7/K8
>        * and P4. It's also good for 386/486s (which actually have
> 16)
>        * as quite a few PCI devices do not support smaller values.
>        */
> +
>       pci_cache_line_size = 32 >> 2;
>       if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
>               pci_cache_line_size = 64 >> 2;  /* K7 & K8 */
>       else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
>               pci_cache_line_size = 128 >> 2; /* P4 */
> +}
> +
> +int __init pcibios_init(void)
> +{
> +     if (!raw_pci_ops) {
> +             printk(KERN_WARNING "PCI: System does not support
> PCI\n");
> +             return 0;
> +     }
>  
> +     pcibios_set_cache_line_size();
>       pcibios_resource_survey();
>  
>       if (pci_bf_sort >= pci_force_bf)

Looks fine.

Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>


-- 
Jesse Barnes, Intel Open Source Technology Center

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