Keir Fraser wrote:
On 13/6/08 16:46, "Jean Guyader" <jean.guyader@xxxxxxxxxxxxx> wrote:
+ /* Do we come from AMD processor ? */
+ if ( data->msr_flags == -1ULL )
+ {
+ data->msr_flags = 0x7ULL;
+
+ data->ldtr_limit = 0xffffffff;
+ data->ldtr_arbytes = 0xc00;
+
+ data->cs_arbytes = 0xc9b;
+
+ data->gs_limit = 0xffffffff;
+ data->gs_arbytes = 0xc00;
+
+ data->tr_arbytes = 0x8b;
+ }
+
It's a bit rude to trample register state like this. Why do limits need to
be forced? The Intel manuals do not specify that any vm-entry checks are
applied to segment limits outside of vm86 mode.
Agreed. The vm-entry check was failing on this one (Intel 3b, 22-11):
- Bit 15 (G). The following checks apply if the register is CS or if
the register is usable:
- If any bit in the limit field in the range 11:0 is 0, G must be 0.
- If any bit in the limit field in the range 31:20 is 1, G must be 1.
--
Jean Guyader
diff -r ec56331c056a xen/arch/x86/hvm/vmx/vmx.c
--- a/xen/arch/x86/hvm/vmx/vmx.c Thu Jun 12 16:34:25 2008 +0100
+++ b/xen/arch/x86/hvm/vmx/vmx.c Mon Jun 16 14:25:33 2008 +0100
@@ -615,6 +615,10 @@ static void vmx_load_cpu_state(struct vc
#ifdef __x86_64__
struct vmx_msr_state *guest_state = &v->arch.hvm_vmx.msr_state;
+ /* Set the msr_flags */
+ if ( data->msr_flags & 0x7ULL )
+ data->msr_flags &= 0x7ULL;
+
/* restore msrs */
guest_state->flags = data->msr_flags;
guest_state->msrs[VMX_INDEX_MSR_LSTAR] = data->msr_lstar;
@@ -624,6 +628,15 @@ static void vmx_load_cpu_state(struct vc
v->arch.hvm_vmx.cstar = data->msr_cstar;
v->arch.hvm_vmx.shadow_gs = data->shadow_gs;
#endif
+
+ /*
+ ** If any bit in the limit field in the range 31:20 is 1,
+ ** G must be set to 1 (Intel 3b, 22-11)
+ **/
+ if ( data->cs_limit & 0xfff0000 )
+ set_bit(11, &data->cs_arbytes);
+ else
+ clear_bit(11, &data->cs_arbytes);
hvm_set_guest_tsc(v, data->tsc);
}
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