RE: [Xen-devel] RE: Question on virtual HPET's behavior

["Shan, Haitao" <haitao.shan@xxxxxxxxx>]

Sorry, I missed one word.

The spec does *not* provide information.

 

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From: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx [mailto:xen-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf Of Shan, Haitao
Sent: 2007年12月26日 22:19
To: Keir Fraser
Cc: xen-devel@xxxxxxxxxxxxxxxxxxx
Subject: [Xen-devel] RE: Question on virtual HPET's behavior

 

No. I did not see such an OS. My concern is: When VAL_SET_CNF is set, do the two registers all get updated? The spec does provide information. From our tests, if you strictly follow the sequence attached in my first mail, the comparator can keep increasing normally. With virtual HPET, it is not true, because period is not considered to be set by only one write. Our tests are carried out on ICH9.

This leads me to confusion. Which one is the right behavior? Writing twice should guarantee the correctness, but is it a must?

 

Haitao Shan

 

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From: Keir Fraser [mailto:Keir.Fraser@xxxxxxxxxxxx]
Sent: 2007年12月26日 21:53
To: Shan, Haitao
Cc: xen-devel@xxxxxxxxxxxxxxxxxxx
Subject: Re: Question on virtual HPET's behavior

 

My reading of the (really bad) specification doc is that in periodic mode writes to the comparator register change the period only, unless VAL_SET_CNF is set in which case only the comparator counter value is set. The Linux HPET code agrees with this interpretation — it writes to the comparator register twice. Do you have an example of an OS that assumes different HPET behaviour?

 -- Keir

On 26/12/07 12:37, "Shan, Haitao" <haitao.shan@xxxxxxxxx> wrote:

Here hpet.period is updated only when timer 0 is in periodic mode and SET_VAL is not set. But from HPET spec 1.0a, I can not find the reason. The spec provides a recommended sequence to reset main counter and comparator.

If the software resets the main counter, the value in the comparator’s value register needs to reset as well. This can be done by setting the n_VAL_SET_CNF bit. Again, to avoid race conditions, this should be done with the main counter halted. The following usage model is expected:

1) Software clears the GLOBAL_ENABLE_CNF bit to prevent any interrupts

2) Software Clears the main counter by writing a value of 00000000h to it.

3) Software sets the TIMER0_VAL_SET_CNF bit.

4) Software writes the new value in the TIMER0_COMPARATOR_VAL register

5) Software sets the GLOBAL_ENABLE_CNF bit to enable interrupts.

What will the result is system software only writes the comparator once after set SET_VAL like the above sequence?

Can you give me some hints? Thanks in advance!

 

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