Re: [Xen-devel] Question about implementation of 32-bit guests on64-bit hypervisor (IDT-related)

[Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>]

On 7/12/07 22:06, "Keir Fraser" <Keir.Fraser@xxxxxxxxxxxx> wrote:

> Yes. I believe that the Intel manuals are incorrect in stating that PAE
> pagetables are restricted to 36-bit addressing. Processors which support
> long mode have their physical address size advertised in CPUID, and I'm
> pretty sure that addresses up to that size can be poked into 8-byte
> pagetable entries whether the pagetable format is 64-bit-mode or pae-mode.
> AMD state explicitly in their manual that PAE pagetables can address up to
> 52 bits, just like 64-bit pagetables, and that this is the architectural
> limit. Furthermore, you guys (Unisys) have done testing on big memory ES7000
> systems (>128GB), and those are Intel boxes -- and I expect some of your
> testing has been 32-bit HVM guests? Given we allocate larger addresses
> first, this would confirm that Intel really does allow addresses >64GB in
> PAE pagetables in practice.

Although Intel SDM Vol 3A Section 3.8 makes it look like PAE only supports
36-bit addressing, the manual simply hasn't been updated properly. There are
various references elsewhere in Vol 3 that make it clear that PAE addressing
is extended on Intel64 processors that have more address lines. The clearest
statement I can find is the second footnote of Section 22.3.1.6 in Vol 3B
(the latest Vol 3B, dated Nov 2007). I'm glad Intel don't hide these details
away. ;-)

 -- Keir



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