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RE: [Xen-devel] Question regarding the number of P2M l3e entries
| To: | "Huang2, Wei" <Wei.Huang2@xxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxx> |
|---|---|
| Subject: | RE: [Xen-devel] Question regarding the number of P2M l3e entries |
| From: | "Ian Pratt" <Ian.Pratt@xxxxxxxxxxxx> |
| Date: | Tue, 3 Apr 2007 10:34:15 +0100 |
| Delivery-date: | Tue, 03 Apr 2007 02:32:11 -0700 |
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| Thread-index: | Acd1uNeEikWwl1aISe2V4WQ5S2lkqwAGeM8g |
| Thread-topic: | [Xen-devel] Question regarding the number of P2M l3e entries |
> In p2m.c (line 197 and line 550), the code assumes the number > of L3 P2M table entries is 8 (under PAE mode). According to > Intel and AMD specs, it is 4. Could someone explain this > discrepancy? Is it a bug? The P2M table maps guest physical addresses to machine addresses. 32b PAE guests may have up to 8GB of RAM on current 32b Xen, hence 8 slots. On 64b Xen you can give them the PAE max of 64GB RAM (in fact, you could actually give them more than 64GB as the physical address width limit no longer applies -- you might have to hack the guest to accept the RAM, though). Ian _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel |
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