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Re: [Xen-devel] Question regarding the number of P2M l3e entries
| To: | "Huang2, Wei" <Wei.Huang2@xxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxx> |
|---|---|
| Subject: | Re: [Xen-devel] Question regarding the number of P2M l3e entries |
| From: | Keir Fraser <Keir.Fraser@xxxxxxxxxxxx> |
| Date: | Tue, 03 Apr 2007 07:33:04 +0100 |
| Delivery-date: | Mon, 02 Apr 2007 23:30:47 -0700 |
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| Thread-index: | Acd1uNeEikWwl1aISe2V4WQ5S2lkqwAARdXv |
| Thread-topic: | [Xen-devel] Question regarding the number of P2M l3e entries |
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See the comment just above line 197. The P2M is a special ‘extended’ PAE pagetable with double the number of top-level slots. This gives PAE guests an 8GB pseudophysical address space. OF course if the P2M is actually used as a shadow pagetable (i.e., because an HVM guest has paging disabled) then only the first four slots will be used for the shadow pagetable, and only the first 4GB of the pseuodphysical address space will be accessible from guest context. -- Keir On 3/4/07 07:25, "Huang2, Wei" <Wei.Huang2@xxxxxxx> wrote: In p2m.c (line 197 and line 550), the code assumes the number of L3 P2M table entries is 8 (under PAE mode). According to Intel and AMD specs, it is 4. Could someone explain this discrepancy? Is it a bug? _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel |
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