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Re: [Xen-devel] Question on shadow_invlpg return value handling.

To: jeet <jeet_sat12@xxxxxxxxxxx>
Subject: Re: [Xen-devel] Question on shadow_invlpg return value handling.
From: Tim Deegan <Tim.Deegan@xxxxxxxxxxxxx>
Date: Tue, 27 Mar 2007 10:29:03 +0000
Cc: xen-devel@xxxxxxxxxxxxxxxxxxx, Tim Deegan <Tim.Deegan@xxxxxxxxxxxxx>, aditya shevalkar <aditya27783@xxxxxxxxxxx>
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At 15:49 +0530 on 27 Mar (1175010562), jeet wrote:
> If on VM entry TLB is flushed why we are handling instruction "invlpg" in xen
> can't this be done by doing VMexit and VM entry as this would do flushing of 
> TLB?

Yes, for now that's true.  When the tagged TLB comes back it won't be;
and after 3.0.5 we might be doing some more optimizations that will need
to hook off the paging_invlpg call.

> Is this TLB flush done due to loading of guest state (mov to cr3)?
> or 
> Is TLB flush on VM entry hardware feature or is implemented in Xen ?


You should really read volume 2 section 15 of the AMD manual, and volume
3a chapters 19-27 of the Intel manuals.


Tim Deegan <Tim.Deegan@xxxxxxxxxxxxx>, XenSource UK Limited
Registered office c/o EC2Y 5EB, UK; company number 05334508

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