Hi Keir, Ian,
Attached is a patch which implements “xm
cpuinfo” and “xm cacheinfo” commands. Output of these
commands on a 4 way paxville (2 core per socket, 2 threads per core) and 2 way
clovertown (Quadcore) system is shown bellow.
It would be easy to extend this functionality
to other architectures such as IA64 or power by reusing most of the code. Other
architectures would need to implement switch-cases XEN_SYSCTL_cpuinfo: &
XEN_SYSCTL_cacheinfo: in their arch_do_sysctl() in the function hyper visor to
get this functionality.
The Changes are distributed in 3 areas viz hyper
visor, libxc and python code as seen in the diffstat bellow.
Please apply and/or provide comments for the patch.
Signed-Off-By: Nitin A Kamble <nitin.a.kamble@xxxxxxxxx>
[nitin@lvmm64 multicore]$ diffstat
multicore_info_patch18.diff
tools/libxc/xc_misc.c
| 37 ++++
tools/libxc/xenctrl.h
| 11 +
tools/python/xen/lowlevel/xc/xc.c
| 139 +++++++++++++++++-
tools/python/xen/util/bugtool.py
| 2
tools/python/xen/xend/XendNode.py
| 8 +
tools/python/xen/xend/server/XMLRPCServer.py
| 3
tools/python/xen/xm/main.py
| 110 ++++++++++++++
xen/arch/x86/cpu/intel_cacheinfo.c
| 208 +++++++++++++++++++++++++++
xen/arch/x86/sysctl.c
| 111 ++++++++++++++
xen/include/public/sysctl.h
| 55 +++++++
10 files changed, 681 insertions(+), 3 deletions(-)
[root@lharwich1-fc4-64 ~]# xm cpuinfo
cpu core package node
id id
id id
0 0 2
ff
1 1 3
ff
2 0 0
ff
3 1 1
ff
4 1 2
ff
5 0 3
ff
6 1 0
ff
7 0 1
ff
8 0 2
ff
9 1 3
ff
a 0 0
ff
b 1 1
ff
c 1 2
ff
d 0 3
ff
e 1 0
ff
f 0 1
ff
[root@lharwich1-fc4-64 ~]# xm cpuinfo -x
cpu core package
node
thread core
id id
id id siblings_map
siblings_map
0
0 2 ff 0000000000000101
0000000000001111
1 1
3 ff 0000000000000202 0000000000002222
2
0 0 ff 0000000000000404
0000000000004444
3
1 1 ff 0000000000000808
0000000000008888
4
1 2 ff 0000000000001010
0000000000001111
5
0 3 ff 0000000000002020
0000000000002222
6
1 0 ff 0000000000004040
0000000000004444
7
0 1 ff 0000000000008080
0000000000008888
8
0 2 ff 0000000000000101
0000000000001111
9
1 3 ff 0000000000000202
0000000000002222
a 0 0
ff 0000000000000404 0000000000004444
b
1 1 ff 0000000000000808
0000000000008888
c
1 2 ff 0000000000001010
0000000000001111
d
0 3 ff 0000000000002020
0000000000002222
e
1 0 ff 0000000000004040 0000000000004444
f
0 1 ff 0000000000008080
0000000000008888
[root@lharwich1-fc4-64 ~]# xm cacheinfo
cpu cache cache cache shared
id level type size cpus_map
0 1 DATA 16KB
00000101
0 2
UNI 1MB 00000101
0 3 UNI
16MB 00001111
1 1 DATA 16KB
00000202
1 2
UNI 1MB 00000202
1 3 UNI
16MB 00002222
2 1 DATA 16KB
00000404
2 2
UNI 1MB 00000404
2 3 UNI
16MB 00004444
3 1 DATA 16KB
00000808
3 2
UNI 1MB 00000808
3 3 UNI
16MB 00008888
4 1 DATA 16KB
00001010
4 2
UNI 1MB 00001010
4 3 UNI
16MB 00001111
5 1 DATA 16KB
00002020
5 2
UNI 1MB 00002020
5 3 UNI
16MB 00002222
6 1 DATA 16KB
00004040
6 2
UNI 1MB 00004040
6 3 UNI
16MB 00004444
7 1 DATA 16KB
00008080
7 2
UNI 1MB 00008080
7 3 UNI
16MB 00008888
8 1 DATA 16KB
00000101
8 2
UNI 1MB 00000101
8 3 UNI
16MB 00001111
9 1 DATA 16KB
00000202
9 2
UNI 1MB 00000202
9 3 UNI
16MB 00002222
a 1 DATA 16KB
00000404
a 2
UNI 1MB 00000404
a 3 UNI
16MB 00004444
b 1 DATA 16KB
00000808
b 2
UNI 1MB 00000808
b 3 UNI
16MB 00008888
c 1 DATA 16KB
00001010
c 2
UNI 1MB 00001010
c 3 UNI
16MB 00001111
d 1 DATA 16KB
00002020
d 2
UNI 1MB 00002020
d 3 UNI
16MB 00002222
e 1 DATA 16KB
00004040
e 2
UNI 1MB 00004040
e 3 UNI
16MB 00004444
f 1 DATA 16KB
00008080
f 2
UNI 1MB 00008080
f 3 UNI
16MB 00008888
[root@lharwich1-fc4-64 ~]# xm cacheinfo -x
cpu cache cache cache shared no_of
ways_of physical
coherency
id level type size cpus_map sets
associativity line_partition line_size
0 1 DATA 16KB
00000101
1f
7
0 3f
0 2
UNI 1MB 00000101
3ff
7
1 3f
0 3 UNI
16MB 00001111 3fff f
0 3f
1 1 DATA 16KB
00000202
1f
7
0 3f
1 2
UNI 1MB 00000202
3ff
7
1 3f
1 3 UNI
16MB 00002222
3fff
f
0 3f
2 1 DATA 16KB
00000404
1f
7
0 3f
2 2
UNI 1MB 00000404
3ff
7
1 3f
2 3 UNI
16MB 00004444
3fff
f
0 3f
3 1 DATA 16KB
00000808
1f
7
0 3f
3 2
UNI 1MB 00000808
3ff
7
1 3f
3 3 UNI
16MB 00008888
3fff
f
0 3f
4 1 DATA 16KB
00001010
1f 7
0 3f
4 2
UNI 1MB 00001010
3ff
7
1 3f
4 3 UNI
16MB 00001111
3fff
f
0 3f
5 1 DATA 16KB
00002020
1f
7
0 3f
5 2
UNI 1MB 00002020
3ff
7
1 3f
5 3 UNI
16MB 00002222
3fff
f
0 3f
6 1 DATA 16KB
00004040
1f
7
0 3f
6 2
UNI 1MB 00004040
3ff
7
1 3f
6 3 UNI
16MB 00004444
3fff
f
0 3f
7 1 DATA 16KB
00008080
1f
7
0 3f
7 2
UNI 1MB 00008080
3ff
7 1
3f
7 3 UNI
16MB 00008888
3fff
f
0 3f
8 1 DATA 16KB
00000101
1f
7
0 3f
8 2
UNI 1MB 00000101
3ff
7
1 3f
8 3 UNI
16MB 00001111
3fff
f
0 3f
9 1 DATA 16KB
00000202
1f
7
0 3f
9 2
UNI 1MB 00000202
3ff
7
1 3f
9 3 UNI
16MB 00002222 3fff f
0 3f
a 1 DATA 16KB
00000404
1f
7
0 3f
a 2
UNI 1MB 00000404
3ff
7
1 3f
a 3 UNI
16MB 00004444
3fff
f
0 3f
b 1 DATA 16KB
00000808
1f
7
0 3f
b 2
UNI 1MB 00000808
3ff
7
1 3f
b 3 UNI
16MB 00008888
3fff
f
0 3f
c 1 DATA 16KB
00001010
1f
7
0 3f
c 2
UNI 1MB 00001010
3ff
7
1 3f
c 3 UNI
16MB 00001111
3fff
f
0 3f
d 1 DATA 16KB
00002020 1f 7
0 3f
d 2
UNI 1MB 00002020
3ff
7
1 3f
d 3 UNI
16MB 00002222
3fff
f
0 3f
e 1 DATA 16KB
00004040
1f
7
0 3f
e 2
UNI 1MB 00004040
3ff
7
1 3f
e 3 UNI
16MB 00004444
3fff
f
0 3f
f 1 DATA 16KB
00008080
1f
7
0 3f
f 2
UNI 1MB 00008080
3ff
7
1 3f
f 3 UNI
16MB 00008888
3fff
f
0 3f
[root@lclovertown1 ~]# xm cpuinfo
cpu core package node
id id
id id
0
0 0 ff
1
0 1 ff
2 1
0 ff
3
1 1 ff
4
2 0 ff
5
2 1 ff
6
3 0 ff
7
3 1 ff
[root@lclovertown1 ~]# xm cpuinfo -x
cpu core package
node
thread core
id id
id id siblings_map
siblings_map
0
0 0 ff 0000000000000001
0000000000000055
1
0 1 ff 0000000000000002
00000000000000aa
2
1 0 ff 0000000000000004
0000000000000055
3
1 1 ff 0000000000000008
00000000000000aa
4
2 0 ff 0000000000000010
0000000000000055
5
2 1 ff 0000000000000020
00000000000000aa
6
3 0 ff 0000000000000040
0000000000000055
7
3 1 ff 0000000000000080
00000000000000aa
[root@lclovertown1 ~]# xm cacheinfo
cpu cache cache cache shared
id level type size cpus_map
0 1 DATA 32KB
00000001
0 1 INST 32KB
00000001
0 2
UNI 4MB 00000005
1 1 DATA 32KB
00000002
1 1 INST 32KB
00000002
1 2
UNI 4MB 0000000a
2 1 DATA 32KB
00000004
2 1 INST 32KB
00000004
2 2
UNI 4MB 00000005
3 1 DATA 32KB
00000008
3 1 INST 32KB
00000008
3 2
UNI 4MB 0000000a
4 1 DATA 32KB
00000010
4 1 INST 32KB
00000010
4 2
UNI 4MB 00000050
5 1 DATA 32KB
00000020
5 1 INST 32KB
00000020
5 2
UNI 4MB 000000a0
6 1 DATA 32KB
00000040
6 1 INST 32KB
00000040
6 2
UNI 4MB 00000050
7 1 DATA 32KB
00000080
7 1 INST 32KB
00000080
7 2
UNI 4MB 000000a0
[root@lclovertown1 ~]# xm cacheinfo -x
cpu cache cache cache shared no_of
ways_of physical
coherency
id level type size cpus_map sets
associativity line_partition line_size
0 1 DATA 32KB
00000001
3f
7
0 3f
0 1 INST 32KB
00000001 3f
7
0 3f
0 2
UNI 4MB 00000005
fff
f
0 3f
1 1 DATA 32KB
00000002
3f
7
0 3f
1 1 INST 32KB
00000002
3f
7
0 3f
1 2
UNI 4MB 0000000a
fff
f
0
3f
2 1 DATA 32KB
00000004
3f
7
0 3f
2 1 INST 32KB
00000004
3f
7
0 3f
2 2
UNI 4MB 00000005
fff
f
0 3f
3 1 DATA 32KB
00000008
3f
7
0 3f
3 1 INST 32KB
00000008
3f
7
0 3f
3 2
UNI 4MB 0000000a
fff
f
0 3f
4 1 DATA 32KB
00000010
3f
7
0 3f
4 1 INST 32KB
00000010
3f
7
0 3f
4 2
UNI 4MB 00000050
fff
f
0 3f
5 1 DATA 32KB
00000020
3f
7
0 3f
5 1 INST 32KB
00000020
3f
7
0 3f
5 2
UNI 4MB 000000a0
fff
f
0 3f
6 1 DATA 32KB
00000040
3f
7
0 3f
6 1 INST 32KB
00000040
3f
7
0 3f
6 2
UNI 4MB 00000050
fff
f
0 3f
7 1 DATA 32KB
00000080 3f
7
0 3f
7 1 INST 32KB
00000080 3f
7
0 3f
7 2
UNI 4MB 000000a0
fff
f
0 3f
Thanks & Regards,
Nitin
Open Source Technology Center, Intel
Corporation.
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