On Mon, Jan 30, 2006 at 12:41:47PM -0800, Jad Naous wrote:
>
>
> Jon Mason wrote:
> >On Thu, Jan 26, 2006 at 12:52:29AM -0800, Jad Naous wrote:
> >>Hi all,
> >>I am exploring the possibility of designing a custom hardware
> >>acceleration solution using an ASIC or an FPGA to accelerate some part
> >>of Xen. Basically, I am looking for some part of the code that could be
> >>built in hardware to make it faster. Does anybody know where I could get
> >>some statistics on the code, such as the most called functions, the most
> >>parallelizable functions, etc... If you could think of something that
> >>would be useful in HW I would be very interested to know.
> >>Thanks,
> >>Jad.
> >
> >You could make a custom NIC FPGA that can handle paravirtulized network
> >receive. The NIC can inspect the destination MAC address of the incoming
> >packet, and DMA it to a pre-alloced space in the domU (removing the need
> >for the page flip). It will require modifying the xen network drivers,
> >but should be pretty cool.
> >
> >Thanks,
> >Jon
>
> Just wanted to update that we are going to implement the paravirtulized
> NIC on an FPGA, and see if you guys can suggest where to start. We have
> never done any XEN development.
By "paravirtulized NIC", I assume you mean one that handles the network
receive in hardware (or are there other features you are planning?).
If so, I would think you would need the following things:
specialized FPGA firmware
custom device driver for FPGA adapter
modified netfront driver (remove page flipping)
modified netback driver
The specialized firmware should have some type of data structure which
contains the MAC address and corresponding DMA address(es) for that
domain. It should be able to parse the MAC header in the adapter cache
and DMA to the corresponding address (without dropping any packets).
The custom device driver should me able to program the adapter with MAC
addresses and DMA addresses (as well as perform generic networking device
driver functionality).
The Xen network drivers (netfront and netback) will have to be modified
to take advantage of this new feature.
I would think you would want to have the basic driver firmware working
as your starting point, then modify it to add the MAC/DMA handling.
Then, modify the xen networking drivers to take advantage.
> The implementation should be done by the end of March. Are there any
An extremely aggressive schedule. Let if there is anything I can do to
help.
> suggestions on how to make our FPGA implementation as portable as
> possible to other boards? The problem is we might end up using some IP
> cores for our implementation. If we have time, we'd get rid of those.
> Thanks,
> Jad.
Helpfully all of this makes sense. If not, feel free to ask me to
clarify.
Thanks,
Jon
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