RE: [Xen-devel] [PATCH] "lock cmpxch8b" and split locks

["Puthiyaparambil, Aravindh" <aravindh.puthiyaparambil@xxxxxxxxxx>]

Keir,

I spoke to our hardware engineers about this. They pointed me at Section
7.1.1 of Volume 3 of the Intel Software Developers Manual.

"Accesses to cacheable memory that are split across bus widths, cache
lines, and page boundaries are not guaranteed to be atomic by the
Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The
Pentium 4, Intel Xeon, and P6 family processors provide bus control
signals that permit external memory subsystems to make split accesses
atomic; however, on aligned data accesses will seriously impact the
performance of the processor and should be avoided."

I hope this gives you a better picture of the situation.

Aravindh

> -----Original Message-----
> From: Keir Fraser [mailto:Keir.Fraser@xxxxxxxxxxxx]
> Sent: Wednesday, October 05, 2005 5:47 PM
> To: Puthiyaparambil, Aravindh
> Cc: Subrahmanian, Raj; Vessey, Bruce A; xen-devel@xxxxxxxxxxxxxxxxxxx;
> Koren, Bradley J
> Subject: Re: [Xen-devel] [PATCH] "lock cmpxch8b" and split locks
> 
> 
> On 5 Oct 2005, at 19:27, Puthiyaparambil, Aravindh wrote:
> 
> > Does anyone know if there are other places where the "lock" prefix
is
> > used with a cache misaligned address?
> 
> x86 systems are supposed to guarantee that LOCKed instructions access
> their memory operand atomically, regardless of alignment (Vol 3 of the
> Intel reference manual). Your systems break this application-visible
> guarantee?
> 
>   -- Keir


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