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xen-ia64-devel
RE: [Xen-ia64-devel] [PATCH] tlb miss handler
> >> Dom0 runs from the very start with vhpt enabled in all
> regions. There should be
> >no alt itlb miss raised from dom0.
> >
> >I thought that dom0 alt itlb miss was intentional because of
> >the explicit region register initial values.
> >It is inconsistent that only dom0 boot time is special.
> >I agree that it is reasonable to modify dom0 start up environment.
>
> Yes current initial rr7 is set with vhpt disabled when dom0
> starts to run, however this region 7 won't be touched since
> dom0 is still in metaphysical mode and then only region 0/4
> is the case there. When dom0 wants to switch to virtual mode,
> move_to_rr will finally falls into set_one_rr and then all
> regions will have vhpt enabled. So even under this case,
> alt_itlb_miss won't happen from dom0.
>
> I think we should modify the initial setting to have all
> regions vhpt enabled, though nothing affected compared to
> current behavior.
I agree that the vhpt should be enabled for all regions for
all domains and the dom0/rr7 behavior should change.
> >> * Why did you only handle cacheable (meant 0xf000....)
> area by identity mapping,
> >whole leaving uncacheable (meant 0xe8000...) area to
> page_fault? That would low
> >down the performance a lot.
> >
> >Misses on the uncacheable area is handled.
> >page_fault() and ia64_do_page_fault() doesn't handle misses
> on the area.
> >If it wasn't handled by dltb miss handler, misses on the
> area would result
> >in dtlb miss/rfi infinite loop.
> >
>
> Yes, you're right. This patch is definitely necessary for
> correctness, and need consideration for incorporation after
> some render.
How frequent are misses on uncacheable pages relative to
misses on cacheable pages? If the ratio if very small
(say one uncacheable miss per 10000 cacheable misses),
it might be best to allow ia64_do_page_fault() to handle
the uncacheable misses as the few extra instructions
to check for uncacheable area might not be worth it.
Obviously this tuning could be done later, but I think it
is wise to justify every instruction in the most frequent
paths and clearly the dtlb miss handler is executed very
frequently.
Dan
Dan
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