At 15:52 +0800 on 09 Jun (1307634772), YAO wrote:
> Hi, I've been reading the code in xen/arch/x86/mm/hap and got some
> 1. Are they the support for intel ept? If so, where is the support for amd
They are the generic support for hardware-assisted paging, i.e. EPT or
RVI. RVI is called NPT in the Xen code (and in the AMD manuals).
> 2. I read the intel manual, it says EPT paging is similar to IA-32e mode
> which has 4 level page. So, if the xen is running under 32bit PAE mode, is
> the ept paging still 4 levels?
> by the way, is dom0 always 32bit pae?
> 3.EPT is used for GPA->HPA, so is the case of p2m(if I remember correctly),
> what's the relationship between them? why do we need p2m when we use hap?
Xen needs to be able to look up gfn->mfn for its own purposes, and the
p2m contains other informatio. like typing. When a domain is using HAP,
its p2m table is stored in the form that the CPU expects for the EPT/RVI
table, so there's no wasted effort or space.
> 4.Can I use ept to control access to some of the guest pages?
Yes. Have a look at the mem_event domctls for a way to do this from
dom0 with callbacks when the guest violates the access controls.
Tim Deegan <Tim.Deegan@xxxxxxxxxx>
Principal Software Engineer, Xen Platform Team
Citrix Systems UK Ltd. (Company #02937203, SL9 0BG)
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