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RE: [Xen-devel] Questions about ept

To: YAO <yffbrave@xxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: RE: [Xen-devel] Questions about ept
From: "Li, Xin" <xin.li@xxxxxxxxx>
Date: Thu, 9 Jun 2011 16:45:36 +0800
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Thread-topic: [Xen-devel] Questions about ept
> Hi, I've been reading the code in xen/arch/x86/mm/hap and got some questions:

> 1. Are they the support for intel ept? If so, where is the support for amd 
> rvi?

hap stands for hardware assisted paging and is an abstract layer for both EPT 
and NPT (i.e. rvi).   You should find some arch specific hooks there too.

> 2. I read the intel manual, it says EPT paging is similar to IA-32e mode 
> which has 4 level page. So, if the xen is running under 32bit PAE mode, is 
> the ept paging still 4 levels?

They are orthogonal.  EPT will be activated only when CPU runs in non-root 
operation while Xen itself runs in root operation.

> by the way, is dom0 always 32bit pae?

No, it can be x86_64.

> 3.EPT is used for GPA->HPA, so is the case of p2m(if I remember correctly), 
> what's the relationship between them? why do we need p2m when we use hap?

p2m is a common virtualization term no matter you use software paging 
(shadow/vTLB) or hardware assisted paging (EPT/NPT).  As you see, software 
paging obviously needs p2m.  Hardware assisted paging incorporates the concept 
of p2m into hardware, but it's still initialized by software.  Xen needs to use 
p2m for guest MMIO emulation even with ept.

> 4.Can I use ept to control access to some of the guest pages?

Yes, each guest page has R(Read)/W(Write)/X(eXecution) permission bits in its 
corresponding EPT entry.

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