WARNING - OLD ARCHIVES

This is an archived copy of the Xen.org mailing list, which we have preserved to ensure that existing links to archives are not broken. The live archive, which contains the latest emails, can be found at http://lists.xen.org/
   
 
 
Xen 
 
Home Products Support Community News
 
   
 

xen-devel

[Xen-devel] RE: [PATCH 3/5] vtdt: Modify vlapic code to add vtdt support

To: "Wei, Gang" <gang.wei@xxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: [Xen-devel] RE: [PATCH 3/5] vtdt: Modify vlapic code to add vtdt support
From: "Wei, Gang" <gang.wei@xxxxxxxxx>
Date: Tue, 14 Dec 2010 18:29:01 +0800
Accept-language: zh-CN, en-US
Acceptlanguage: zh-CN, en-US
Cc: "Wei, Gang" <gang.wei@xxxxxxxxx>, Keir Fraser <keir.fraser@xxxxxxxxxxxxx>, Tim Deegan <Tim.Deegan@xxxxxxxxxx>
Delivery-date: Tue, 14 Dec 2010 02:29:51 -0800
Envelope-to: www-data@xxxxxxxxxxxxxxxxxxx
In-reply-to: <F26D193E20BBDC42A43B611D1BDEDE7124EADAFA5E@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>
List-help: <mailto:xen-devel-request@lists.xensource.com?subject=help>
List-id: Xen developer discussion <xen-devel.lists.xensource.com>
List-post: <mailto:xen-devel@lists.xensource.com>
List-subscribe: <http://lists.xensource.com/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=subscribe>
List-unsubscribe: <http://lists.xensource.com/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=unsubscribe>
References: <F26D193E20BBDC42A43B611D1BDEDE7124EADAFA5E@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>
Sender: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
Thread-index: AcubPslPXD79XKNoRpanX8il5iAsXgAOnVGQ
Thread-topic: [PATCH 3/5] vtdt: Modify vlapic code to add vtdt support
Resend.

vtdt: Modify vlapic code to add vtdt support

Accesses to MSR_IA32_TSC_DEADLINE are trapped, with value stored in a new field 
vlapic->hw.tdt_msr. vlapic->pt is reused in one shot mode for vtdt to trigger 
expire events.

For details, please refer to the Intel Architectures Software Developer's 
Manual 3A, 10.5.4.1 TSC-Deadline Mode.

Signed-off-by: Wei Gang <gang.wei@xxxxxxxxx>

diff -r 41b85041d655 xen/arch/x86/hvm/hvm.c
--- a/xen/arch/x86/hvm/hvm.c    Wed Dec 15 23:31:41 2010 +0800
+++ b/xen/arch/x86/hvm/hvm.c    Wed Dec 15 23:31:44 2010 +0800
@@ -2235,6 +2235,10 @@ int hvm_msr_read_intercept(unsigned int 
             goto gp_fault;
         break;
 
+    case MSR_IA32_TSC_DEADLINE:
+        *msr_content = vlapic_tdt_msr_get(vcpu_vlapic(v));
+        break;
+
     case MSR_IA32_CR_PAT:
         *msr_content = v->arch.hvm_vcpu.pat_cr;
         break;
@@ -2340,6 +2344,10 @@ int hvm_msr_write_intercept(unsigned int
 
     case MSR_IA32_APICBASE:
         vlapic_msr_set(vcpu_vlapic(v), msr_content);
+        break;
+
+    case MSR_IA32_TSC_DEADLINE:
+        vlapic_tdt_msr_set(vcpu_vlapic(v), msr_content);
         break;
 
     case MSR_IA32_APICBASE_MSR ... MSR_IA32_APICBASE_MSR + 0x3ff:
diff -r 41b85041d655 xen/arch/x86/hvm/vlapic.c
--- a/xen/arch/x86/hvm/vlapic.c Wed Dec 15 23:31:41 2010 +0800
+++ b/xen/arch/x86/hvm/vlapic.c Thu Dec 16 00:16:13 2010 +0800
@@ -56,7 +56,7 @@ static unsigned int vlapic_lvt_mask[VLAP
 static unsigned int vlapic_lvt_mask[VLAPIC_LVT_NUM] =
 {
      /* LVTT */
-     LVT_MASK | APIC_LVT_TIMER_PERIODIC,
+     LVT_MASK | APIC_TIMER_MODE_MASK,
      /* LVTTHMR */
      LVT_MASK | APIC_MODE_MASK,
      /* LVTPC */
@@ -79,7 +79,16 @@ static unsigned int vlapic_lvt_mask[VLAP
     (vlapic_get_reg(vlapic, lvt_type) & APIC_MODE_MASK)
 
 #define vlapic_lvtt_period(vlapic)                              \
-    (vlapic_get_reg(vlapic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC)
+    ((vlapic_get_reg(vlapic, APIC_LVTT) & APIC_TIMER_MODE_MASK) \
+     == APIC_TIMER_MODE_PERIODIC)
+
+#define vlapic_lvtt_oneshot(vlapic)                             \
+    ((vlapic_get_reg(vlapic, APIC_LVTT) & APIC_TIMER_MODE_MASK) \
+     == APIC_TIMER_MODE_ONESHOT)
+
+#define vlapic_lvtt_tdt(vlapic)                                 \
+    ((vlapic_get_reg(vlapic, APIC_LVTT) & APIC_TIMER_MODE_MASK) \
+     == APIC_TIMER_MODE_TSC_DEADLINE)
 
 
 /*
@@ -481,9 +490,20 @@ static void vlapic_read_aligned(
         break;
 
     case APIC_TMCCT: /* Timer CCR */
+        if ( !vlapic_lvtt_oneshot(vlapic) && !vlapic_lvtt_period(vlapic) )
+        {
+            *result = 0;
+            break;
+        }
         *result = vlapic_get_tmcct(vlapic);
         break;
 
+    case APIC_TMICT: /* Timer ICR */
+        if ( !vlapic_lvtt_oneshot(vlapic) && !vlapic_lvtt_period(vlapic) )
+        {
+            *result = 0;
+            break;
+        }
     default:
         *result = vlapic_get_reg(vlapic, offset);
         break;
@@ -566,6 +586,12 @@ static void vlapic_pt_cb(struct vcpu *v,
     *(s_time_t *)data = hvm_get_guest_time(v);
 }
 
+static void vlapic_tdt_pt_cb(struct vcpu *v, void *data)
+{
+    *(s_time_t *)data = hvm_get_guest_time(v);
+    vcpu_vlapic(v)->hw.tdt_msr = 0;
+}
+
 static int vlapic_reg_write(struct vcpu *v,
                             unsigned int offset, unsigned long val)
 {
@@ -657,6 +683,14 @@ static int vlapic_reg_write(struct vcpu 
         break;
 
     case APIC_LVTT:         /* LVT Timer Reg */
+        if ( (vlapic_get_reg(vlapic, offset) & APIC_TIMER_MODE_MASK) !=
+             (val & APIC_TIMER_MODE_MASK) )
+        {
+            destroy_periodic_time(&vlapic->pt);
+            vlapic_set_reg(vlapic, APIC_TMICT, 0);
+            vlapic_set_reg(vlapic, APIC_TMCCT, 0);
+            vlapic->hw.tdt_msr = 0;
+        }
         vlapic->pt.irq = val & APIC_VECTOR_MASK;
     case APIC_LVTTHMR:      /* LVT Thermal Monitor */
     case APIC_LVTPC:        /* LVT Performance Counter */
@@ -680,6 +714,9 @@ static int vlapic_reg_write(struct vcpu 
     {
         uint64_t period;
 
+        if ( !vlapic_lvtt_oneshot(vlapic) && !vlapic_lvtt_period(vlapic) )
+            break;
+
         vlapic_set_reg(vlapic, APIC_TMICT, val);
         if ( val == 0 )
         {
@@ -842,6 +879,73 @@ void vlapic_msr_set(struct vlapic *vlapi
 
     HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
                 "apic base msr is 0x%016"PRIx64, vlapic->hw.apic_base_msr);
+}
+
+uint64_t  vlapic_tdt_msr_get(struct vlapic *vlapic)
+{
+    if ( !vlapic_lvtt_tdt(vlapic) )
+        return 0;
+
+    return vlapic->hw.tdt_msr;
+}
+
+void vlapic_tdt_msr_set(struct vlapic *vlapic, uint64_t value)
+{
+    uint64_t guest_tsc;
+    uint64_t guest_time;
+    struct vcpu *v = vlapic_vcpu(vlapic);
+
+    /* may need to exclude some other conditions like vlapic->hw.disabled */
+    if ( !vlapic_lvtt_tdt(vlapic) )
+    {
+        HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER, "ignore tsc deadline msr write");
+        return;
+    }
+    
+    /* new_value = 0, >0 && <= now, > now */
+    guest_tsc = hvm_get_guest_tsc(v);
+    guest_time = hvm_get_guest_time(v);
+    if ( value > guest_tsc )
+    {
+        uint64_t delta = value - v->arch.hvm_vcpu.cache_tsc_offset;
+        delta = gtsc_to_gtime(v->domain, delta);
+        delta = max_t(s64, delta - guest_time, 0);
+
+        HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER, "delta[0x%016"PRIx64"]", delta);
+
+        vlapic->hw.tdt_msr = value;
+        /* .... reprogram tdt timer */
+        create_periodic_time(v, &vlapic->pt, delta, 0,
+                             vlapic->pt.irq, vlapic_tdt_pt_cb,
+                             &vlapic->timer_last_update);
+        vlapic->timer_last_update = vlapic->pt.last_plt_gtime;
+    }
+    else
+    {
+        vlapic->hw.tdt_msr = 0;
+
+        /* trigger a timer event if needed */
+        if ( value > 0 )
+        {
+            create_periodic_time(v, &vlapic->pt, 0, 0,
+                                 vlapic->pt.irq, vlapic_tdt_pt_cb,
+                                 &vlapic->timer_last_update);
+            vlapic->timer_last_update = vlapic->pt.last_plt_gtime;
+        }
+        else
+        {
+            /* .... stop tdt timer */
+            destroy_periodic_time(&vlapic->pt);
+        }
+
+        HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER, "value[0x%016"PRIx64"]", value);
+    }
+
+    HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER,
+                "tdt_msr[0x%016"PRIx64"],"
+                " gtsc[0x%016"PRIx64"],"
+                " gtime[0x%016"PRIx64"]",
+                vlapic->hw.tdt_msr, guest_tsc, guest_time);
 }
 
 static int __vlapic_accept_pic_intr(struct vcpu *v)
@@ -956,6 +1060,17 @@ void vlapic_reset(struct vlapic *vlapic)
     destroy_periodic_time(&vlapic->pt);
 }
 
+static void lapic_tdt_rearm(struct vlapic *s)
+{
+    uint64_t tdt_msr = vlapic_tdt_msr_get(s);
+
+    s->pt.irq = vlapic_get_reg(s, APIC_LVTT) & APIC_VECTOR_MASK;
+    if ( tdt_msr == 0)
+       return;
+
+    vlapic_tdt_msr_set(s, tdt_msr);
+}
+
 /* rearm the actimer if needed, after a HVM restore */
 static void lapic_rearm(struct vlapic *s)
 {
@@ -1023,7 +1138,7 @@ static int lapic_load_hidden(struct doma
     }
     s = vcpu_vlapic(v);
     
-    if ( hvm_load_entry(LAPIC, h, &s->hw) != 0 ) 
+    if ( hvm_load_entry_zeroextend(LAPIC, h, &s->hw) != 0 ) 
         return -EINVAL;
 
     vmx_vlapic_msr_changed(v);
@@ -1050,7 +1165,10 @@ static int lapic_load_regs(struct domain
         return -EINVAL;
 
     vlapic_adjust_i8259_target(d);
-    lapic_rearm(s);
+    if ( vlapic_lvtt_tdt(s) )
+        lapic_tdt_rearm(s);
+    else
+        lapic_rearm(s);
     return 0;
 }
 
diff -r 41b85041d655 xen/include/asm-x86/hvm/vlapic.h
--- a/xen/include/asm-x86/hvm/vlapic.h  Wed Dec 15 23:31:41 2010 +0800
+++ b/xen/include/asm-x86/hvm/vlapic.h  Wed Dec 15 23:31:44 2010 +0800
@@ -92,6 +92,8 @@ void vlapic_reset(struct vlapic *vlapic)
 void vlapic_reset(struct vlapic *vlapic);
 
 void vlapic_msr_set(struct vlapic *vlapic, uint64_t value);
+void vlapic_tdt_msr_set(struct vlapic *vlapic, uint64_t value);
+uint64_t vlapic_tdt_msr_get(struct vlapic *vlapic);
 
 int vlapic_accept_pic_intr(struct vcpu *v);
 
diff -r 41b85041d655 xen/include/public/arch-x86/hvm/save.h
--- a/xen/include/public/arch-x86/hvm/save.h    Wed Dec 15 23:31:41 2010 +0800
+++ b/xen/include/public/arch-x86/hvm/save.h    Wed Dec 15 23:31:44 2010 +0800
@@ -265,6 +265,7 @@ struct hvm_hw_lapic {
     uint64_t             apic_base_msr;
     uint32_t             disabled; /* VLAPIC_xx_DISABLED */
     uint32_t             timer_divisor;
+    uint64_t             tdt_msr;
 };
 
 DECLARE_HVM_SAVE_TYPE(LAPIC, 5, struct hvm_hw_lapic);

Attachment: 4-vtdt.patch
Description: 4-vtdt.patch

_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-devel