RE: [Xen-devel] [PATCH] mask cpuid TSC invariant bit for various circumstances (Take 2)

[Dan Magenheimer <dan.magenheimer@xxxxxxxxxx>]

> On 06/11/2009 14:23, "Dan Magenheimer" 
> <dan.magenheimer@xxxxxxxxxx> wrote:
> 
> >> I think I pushed you into changing this in a way I like even
> >> less. :-) I can
> >> live with your original patch, so I'll check that in after all.
> >> 
> >>  -- Keir
> > 
> > But note that you were correct that the original patch
> > didn't work with HVM domains, I presume because the xc cpuid
> > policy code doesn't initialize 0x80000007.  That's why
> > I pulled the code out of the loop in domain_cpuid and
> > then entirely out to time.c
> 
> Even if it didn't initialise 0x80000007 --- which actually I 
> am sure it
> does, as DEF_MAX_EXT is defined as 0x80000008 in 
> xc_cpuid_x86.c --- then the
> result will be we return all zeroes for that leaf. And that's 
> safe. So I
> think the original patch is fine for HVM guests too.
> 
>  -- Keir

Thought I'd wait until the final patch showed up in xen-unstable
so I could test it before shooting off my mouth ;-)

With the original (and your checked in) patch, it appears
that the Invariant TSC bit is *always* zero for hvm.  One of
the points of the patch was to leave it unmasked (i.e.
pass it through unchanged) under certain conditions.

So... I think we need another patch now in xc_cpuid_x86.

diff -r 42e268da38b9 tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c        Mon Nov 09 08:19:55 2009 +0000
+++ b/tools/libxc/xc_cpuid_x86.c        Mon Nov 09 11:13:58 2009 -0700
@@ -237,6 +237,7 @@ static void xc_cpuid_hvm_policy(
     case 0x80000004: /* ... continued         */
     case 0x80000005: /* AMD L1 cache/TLB info (dumped by Intel policy) */
     case 0x80000006: /* AMD L2/3 cache/TLB info ; Intel L2 cache features */
+    case 0x80000007: /* Intel/AMD Power Management (e.g. Invariant TSC) */
         break;
 
     default:

xc_cpuid.patch
Description: Binary data

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