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RE: [Xen-devel] million cycle interrupt

To: Keir Fraser <keir.fraser@xxxxxxxxxxxxx>, "Tian, Kevin" <kevin.tian@xxxxxxxxx>, "Xen-Devel (E-mail)" <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: RE: [Xen-devel] million cycle interrupt
From: Dan Magenheimer <dan.magenheimer@xxxxxxxxxx>
Date: Tue, 14 Apr 2009 15:38:52 +0000 (GMT)
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> You could validate that quite easily by adding your own timer 
> read wrapped
> in TSC reads. Actually a PIT read, even though it requires 
> multiple accesses
> over the ISA bus, should take less than 10us.

I'll take a look at that next.  Taking average as
well as max, the timer_interrupt interrupt is
AVERAGING over 300K cycles (with 8 processors).
This interrupt is 100Hz, correct?  If so, that means
a full 1% of one processor's cycles are spent
processing timer_interrupts!

The MSI interrupts have large max, but the average
is relatively small (under 5000 cycles). It still
would be nice to know what is causing the max
value, especially since it only occurs for me with
more than 4 processors.

But first, Keir, would you take this patch so that this
kind of issue can be more easily diagnosed in the future?
If you're worried about the extra two global variable
reads, you could wrap an "#ifndef NDEBUG" around it
(with #else #define opt_measure_irqs 0), but it might
be nice to have this diagnostic capability in released

Attachment: measure_irq.patch
Description: Binary data

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