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xen-devel
Re: [Xen-devel] million cycle interrupt
On 14/04/2009 05:23, "Dan Magenheimer" <dan.magenheimer@xxxxxxxxxx> wrote:
>> If it's really caused by SMT, it's more likely to be software
>> caused resource contention due to doubled logical processors.
>
> You mentioned PIT earlier... I wonder if PIT can be
> read in parallel if read from different cores, but
> if read from different threads, it must be serialized?
> A million cycles is probably about right for a platform
> timer read, true?
You could validate that quite easily by adding your own timer read wrapped
in TSC reads. Actually a PIT read, even though it requires multiple accesses
over the ISA bus, should take less than 10us.
-- Keir
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- Re: [Xen-devel] million cycle interrupt, (continued)
- Re: [Xen-devel] million cycle interrupt, Keir Fraser
- RE: [Xen-devel] million cycle interrupt, Dan Magenheimer
- RE: [Xen-devel] million cycle interrupt, Tian, Kevin
- RE: [Xen-devel] million cycle interrupt, Dan Magenheimer
- RE: [Xen-devel] million cycle interrupt, Tian, Kevin
- RE: [Xen-devel] million cycle interrupt, Dan Magenheimer
- RE: [Xen-devel] million cycle interrupt, Tian, Kevin
- RE: [Xen-devel] million cycle interrupt, Dan Magenheimer
- RE: [Xen-devel] million cycle interrupt, Tian, Kevin
- RE: [Xen-devel] million cycle interrupt, Dan Magenheimer
- Re: [Xen-devel] million cycle interrupt,
Keir Fraser <=
- RE: [Xen-devel] million cycle interrupt, Dan Magenheimer
- RE: [Xen-devel] million cycle interrupt, Dan Magenheimer
- RE: [Xen-devel] million cycle interrupt, Tian, Kevin
RE: [Xen-devel] million cycle interrupt, Puthiyaparambil, Aravindh
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