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Re: [Xen-devel] vmx & efer

>>> Keir Fraser <Keir.Fraser@xxxxxxxxxxxx> 07.05.07 11:00 >>>
>On 7/5/07 09:57, "Jan Beulich" <jbeulich@xxxxxxxxxx> wrote:
>>> You seem to be assuming that if the hypervisor executes with 4-level
>>> pagetables then so must all VMX guests. This isn't true. A VMX VCPU running
>>> in 32-bit mode (PAE or not) will execute with 3-level pagetables when
>>> running on x86/64 Xen.
>> Oh, okay, I didn't realize that. That makes things look consistent again, as
>> long
>> as you are saying that in this mode the physical CR3 continues to be a 64-bit
>> register?
>That I'm not sure about. We always ensure the shadow PAE CR3 is in low 4GB,
>so we don't have to worry about this. I guess it depends whether PAE CR3 is

Because it happens to sit in the vcpu structure? That's one more thing to
remember when folding the Xen heap into the domain heap on x86-64 then.
(I have to admit that I dislike all these hidden address range dependencies.)

>32-bit because of microarchitectural assumptions, or merely because in
>32-bit mode there is no way to write more than 32 bits to a control


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