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Re: [Xen-devel] vmx & efer

To: Jan Beulich <jbeulich@xxxxxxxxxx>, Jun Nakajima <jun.nakajima@xxxxxxxxx>
Subject: Re: [Xen-devel] vmx & efer
From: Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>
Date: Mon, 07 May 2007 09:43:44 +0100
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On 7/5/07 09:35, "Jan Beulich" <jbeulich@xxxxxxxxxx> wrote:

>> The bit LMA and LME are automaticaly are loaded by the hardware. Please
>> look at the spec (Volume 3B).
> Hmm, that cannot be fully true. The description for bit 9 of the VM-Entry
> control field says: "Its value is loaded into IA32_EFER.LMA and IA32_EFER.LME
> as part of VM entry." However, even if the bit is clear the processor must
> remain in 4-level paging mode, and unless I'm missing something there's no
> separation between a bit controlling long mode in terms of the effect the
> L-bit of a code descriptor has (and e.g. requiring 64-bit gates in descriptor
> tables) and a bit controlling the paging mode. So in reality there must be
> two bits (and hence neither of them can be considered EFER.LME or EFER.LMA).

You seem to be assuming that if the hypervisor executes with 4-level
pagetables then so must all VMX guests. This isn't true. A VMX VCPU running
in 32-bit mode (PAE or not) will execute with 3-level pagetables when
running on x86/64 Xen.

 -- Keir

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