[PATCH v8 12/26] emul/ns16x50: implement FCR register (write-only)

[dmukhin@xxxxxxxx]

From: Denis Mukhin <dmukhin@xxxxxxxx>

Add emulation logic for FCR register.

Note, that does not hook FIFO interrupt moderation to the FIFO
management code for simplicity.

Signed-off-by: Denis Mukhin <dmukhin@xxxxxxxx>
---
 xen/common/emul/vuart/ns16x50.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index 8d3845a8a4cd..404e12311090 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -436,6 +436,39 @@ static int ns16x50_io_write8(
         }
         break;
 
+    case UART_FCR: /* WO */
+        if ( val & UART_FCR_RSRVD0 )
+            ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
+                         UART_FCR_RSRVD0);
+
+        if ( val & UART_FCR_RSRVD1 )
+            ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
+                         UART_FCR_RSRVD1);
+
+        if ( val & UART_FCR_CLRX )
+        {
+            ns16x50_fifo_rx_reset(vdev);
+            regs[UART_LSR] &= ~UART_LSR_DR;
+        }
+
+        if ( val & UART_FCR_CLTX )
+        {
+            ns16x50_fifo_tx_reset(vdev);
+
+            regs[UART_LSR] |= UART_LSR_THRE | UART_LSR_TEMT;
+            vdev->thr_pending = true;
+        }
+
+        if ( val & UART_FCR_ENABLE )
+            val &= UART_FCR_ENABLE | UART_FCR_DMA |
+                   UART_FCR_RTB0 | UART_FCR_RTB1;
+        else
+            val = 0;
+
+        regs[UART_FCR] = val;
+
+        break;
+
     case UART_LCR:
         regs[UART_LCR] = val;
         break;
-- 
2.56.0