[PATCH v8 07/26] emul/ns16x50: implement IER/IIR registers

[dmukhin@xxxxxxxx]

From: Denis Mukhin <dmukhin@xxxxxxxx>

Add interrupt enable register emulation (IER) and interrupt identity
reason (IIR) register emulation to the I/O port handler.

Also add routines for asserting/deasserting the virtual ns16x50
interrupt line as a dependent on IIR code. Add vPIC handling (HVM).

Latch the interrupt line state to avoid poke ns16x50_irq_check() on
every I/O register access.

Signed-off-by: Denis Mukhin <dmukhin@xxxxxxxx>
---
 xen/common/emul/vuart/ns16x50.c | 112 ++++++++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index 2371aa32d03f..7c5cdc99cfa7 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -88,6 +88,7 @@ struct vuart_ns16x50 {
     const char *name;                   /* Device name */
     spinlock_t lock;                    /* Protection */
     struct xencons_interface cons;      /* Emulated RX/TX FIFOs */
+    bool irq_asserted;                  /* IRQ line status */
 };
 
 static inline void ns16x50_lock_init(struct vuart_ns16x50 *vdev)
@@ -113,6 +114,101 @@ static inline void ns16x50_unlock(struct vuart_ns16x50 
*vdev,
     spin_unlock(&vdev->lock);
 }
 
+static bool cf_check ns16x50_iir_check_lsi(const struct vuart_ns16x50 *vdev)
+{
+    return false;
+}
+
+static bool cf_check ns16x50_iir_check_rda(const struct vuart_ns16x50 *vdev)
+{
+    return false;
+}
+
+static bool cf_check ns16x50_iir_check_thr(const struct vuart_ns16x50 *vdev)
+{
+    return false;
+}
+
+static bool cf_check ns16x50_iir_check_msi(const struct vuart_ns16x50 *vdev)
+{
+    return false;
+}
+
+/*
+ * Get the interrupt identity reason.
+ *
+ * IIR is re-calculated once called, because ns16x50 always reports high
+ * priority events first.
+ */
+static uint8_t ns16x50_iir_get(const struct vuart_ns16x50 *vdev)
+{
+    /*
+     * Interrupt identity reasons by priority.
+     * NB: high priority are at lower indexes below.
+     */
+    static const struct {
+        bool (*check)(const struct vuart_ns16x50 *vdev);
+        uint8_t ier;
+        uint8_t iir;
+    } iir_by_prio[] = {
+        [0] = { ns16x50_iir_check_lsi, UART_IER_ELSI,   UART_IIR_LSI },
+        [1] = { ns16x50_iir_check_rda, UART_IER_ERDAI,  UART_IIR_RDA },
+        [2] = { ns16x50_iir_check_thr, UART_IER_ETHREI, UART_IIR_THR },
+        [3] = { ns16x50_iir_check_msi, UART_IER_EMSI,   UART_IIR_MSI },
+    };
+    const uint8_t *regs = vdev->regs;
+    uint8_t iir = 0;
+    unsigned int i;
+
+    for ( i = 0; i < ARRAY_SIZE(iir_by_prio); i++ )
+    {
+        if ( (regs[UART_IER] & iir_by_prio[i].ier) &&
+             iir_by_prio[i].check(vdev) )
+            break;
+
+    }
+    if ( i == ARRAY_SIZE(iir_by_prio) )
+        iir |= UART_IIR_NOINT;
+    else
+        iir |= iir_by_prio[i].iir;
+
+    if ( regs[UART_FCR] & UART_FCR_ENABLE )
+        iir |= UART_IIR_FE;
+
+    return iir;
+}
+
+/*
+ * Assert/deassert virtual ns16x50 interrupt line.
+ */
+static void ns16x50_irq_check(struct vuart_ns16x50 *vdev)
+{
+    const struct vuart_info *info = vdev->info;
+    struct domain *d = vdev->owner;
+    uint8_t iir = ns16x50_iir_get(vdev);
+    bool asserted = !(iir & UART_IIR_NOINT);
+
+    if ( asserted == vdev->irq_asserted )
+        return;
+
+    vdev->irq_asserted = asserted;
+
+    if ( has_vpic(d) )
+    {
+        if ( asserted )
+            hvm_isa_irq_assert(d, info->irq, vioapic_get_vector);
+        else
+            hvm_isa_irq_deassert(d, info->irq);
+    }
+    else
+        ASSERT_UNREACHABLE();
+
+    ns16x50_debug(vdev, "IRQ#%d IIR %#02x %s\n",
+                  info->irq,
+                  iir,
+                  asserted ? "assert" : "deassert");
+}
+
 /*
  * Emulate 8-bit write access to ns16x50 register.
  */
@@ -143,6 +239,10 @@ static int ns16x50_io_write8(
             regs[NS16X50_REGS_NUM + UART_DLM] = val;
         }
         /* DLAB=0 */
+        else
+        {
+            regs[UART_IER] = val & UART_IER_ALL_INTR;
+        }
         break;
 
     /* NB: Firmware (e.g. OVMF) may rely on SCR presence. */
@@ -155,6 +255,8 @@ static int ns16x50_io_write8(
         break;
     }
 
+    ns16x50_irq_check(vdev);
+
     return rc;
 }
 
@@ -237,6 +339,11 @@ static int ns16x50_io_read8(
         }
 
         /* DLAB=0 */
+        val = regs[UART_IER];
+        break;
+
+    case UART_IIR: /* RO */
+        val = ns16x50_iir_get(vdev);
         break;
 
     case UART_SCR:
@@ -250,6 +357,8 @@ static int ns16x50_io_read8(
 
     *data = val;
 
+    ns16x50_irq_check(vdev);
+
     return rc;
 }
 
@@ -398,6 +507,7 @@ static void ns16x50_reset(struct vuart_ns16x50 *vdev)
     const uint16_t divisor = (UART_CLOCK_HZ / 115200) >> 4;
 
     memset(vdev->regs, 0, sizeof(vdev->regs));
+    vdev->irq_asserted = false;
 
     /* NB: report 115200 baud rate. */
     vdev->regs[NS16X50_REGS_NUM + UART_DLL] = divisor & UINT8_MAX;
@@ -428,6 +538,8 @@ static int ns16x50_init(void *arg)
 
     ns16x50_reset(vdev);
 
+    ns16x50_irq_check(vdev);
+
     return 0;
 }
 
-- 
2.56.0