[PATCH v4 28/28] x86emul: enable outer product insns for ACE

[Jan Beulich <jbeulich@xxxxxxxx>]

While they're different from TMUL ones in terms of operands used, they
similarly don't access memory. Hence there's little difference for our
purposes, and the logic ends up being pretty similar.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
SDE: ???
---
v4: New.

--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -21,6 +21,7 @@ The format is based on [Keep a Changelog
    - Support for AVX10-V2-AUX. (Experimental)
    - Support for APX. (Experimental)
    - Support for AMX and XFD. (Experimental)
+   - Support for ACE. (Experimental)
 
 ### Removed
  - On Arm:
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -1979,6 +1979,11 @@ static const struct evex {
     { { 0x59 }, 2, T, R, pfx_66, Wn, Ln }, /* vbroadcast32x2 / vpbroadcastq */
     { { 0x5a }, 2, F, R, pfx_66, Wn, L1|L2 }, /* vbroadcasti{32x4,64x2} */
     { { 0x5b }, 2, F, R, pfx_66, Wn, L2 }, /* vbroadcasti{32x8,64x4} */
+    { { 0x5c, 0xc0 }, 2, F, N, pfx_f3, W0, L2 }, /* top2bf16ps */
+    { { 0x5e, 0xc0 }, 2, F, N, pfx_no, W0, L2 }, /* top4buud */
+    { { 0x5e, 0xc0 }, 2, F, N, pfx_66, W0, L2 }, /* top4busd */
+    { { 0x5e, 0xc0 }, 2, F, N, pfx_f3, W0, L2 }, /* top4bsud */
+    { { 0x5e, 0xc0 }, 2, F, N, pfx_f2, W0, L2 }, /* top4bssd */
     { { 0x62 }, 2, T, R, pfx_66, Wn, Ln }, /* vpexpand{b,w} */
     { { 0x63 }, 2, T, W, pfx_66, Wn, Ln }, /* vpcompress{b,w} */
     { { 0x64 }, 2, T, R, pfx_66, Wn, Ln }, /* vpblendm{d,q} */
@@ -2179,6 +2184,11 @@ static const struct evex {
     { { 0x73 }, 3, T, R, pfx_66, Wn, Ln }, /* vshrd{d,q} */
     { { 0x77, 0xc0 }, 3, F, N, pfx_f3, W0, L2 }, /* tcvtrowps2bf16l */
     { { 0x77, 0xc0 }, 3, F, N, pfx_f2, W0, L2 }, /* tcvtrowps2phl */
+    { { 0x8d, 0xc0 }, 3, F, N, pfx_no, W0, L2 }, /* top4mxbf8ps */
+    { { 0x8d, 0xc0 }, 3, F, N, pfx_66, W0, L2 }, /* top4mxhf8ps */
+    { { 0x8d, 0xc0 }, 3, F, N, pfx_f3, W0, L2 }, /* top4mxhbf8ps */
+    { { 0x8d, 0xc0 }, 3, F, N, pfx_f2, W0, L2 }, /* top4mxbhf8ps */
+    { { 0x8f, 0xc0 }, 3, F, N, pfx_f2, W0, L2 }, /* top4mxbssps */
     { { 0xc2 }, 3, T, R, pfx_no, W0, Ln }, /* vcmpph */
     { { 0xc2 }, 3, T, R, pfx_f3, W0, LIG }, /* vcmpsh */
     { { 0xc2 }, 3, T, R, pfx_f2, W0, Ln }, /* vcmpbf16 */
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -531,6 +531,8 @@ static const struct ext0f3a_table {
     [0x7a ... 0x7b] = { .simd_size = simd_scalar_opc, .four_op = 1 },
     [0x7c ... 0x7d] = { .simd_size = simd_packed_fp, .four_op = 1 },
     [0x7e ... 0x7f] = { .simd_size = simd_scalar_opc, .four_op = 1 },
+    [0x8d] = { .simd_size = simd_other },
+    [0x8f] = { .simd_size = simd_other },
     [0xc2] = { .simd_size = simd_any_fp, .d8s = d8s_vl },
     [0xcc] = { .simd_size = simd_other },
     [0xce ... 0xcf] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -7206,6 +7206,27 @@ x86_emulate(
         goto simd_0f_common;
     }
 
+    case X86EMUL_OPC_EVEX_F3(0x0f38, 0x5c): /* top2bf16ps zmm,zmm,tmm */
+    case X86EMUL_OPC_EVEX   (0x0f38, 0x5e): /* top4buud zmm,zmm,tmm */
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x5e): /* top4busd zmm,zmm,tmm */
+    case X86EMUL_OPC_EVEX_F3(0x0f38, 0x5e): /* top4bsud zmm,zmm,tmm */
+    case X86EMUL_OPC_EVEX_F2(0x0f38, 0x5e): /* top4bssd zmm,zmm,tmm */
+        if ( ea.type != OP_REG )
+            goto unrecognized_insn;
+        generate_exception_if((!mode_64bit() || evex.lr != 2 || evex.opmsk ||
+                               evex.brs || evex.w),
+                              X86_EXC_UD);
+        vcpu_must_have(ace);
+
+        get_fpu(X86EMUL_FPU_zmm_ace);
+        sttilecfg(&mmvalp->tilecfg);
+        generate_exception_if(!tile_valid(modrm_reg, &mmvalp->tilecfg,
+                                          PALETTE(ACE)),
+                              X86_EXC_UD);
+
+        op_bytes = 1; /* fake */
+        goto simd_0f_common;
+
     case X86EMUL_OPC_EVEX_66(0x0f38, 0x62): /* vpexpand{b,w} 
[xyz]mm/mem,[xyz]mm{k} */
     case X86EMUL_OPC_EVEX_66(0x0f38, 0x63): /* vpcompress{b,w} 
[xyz]mm,[xyz]mm/mem{k} */
         visa_check(_vbmi2);
@@ -9010,6 +9031,32 @@ x86_emulate(
         visa_check(_vbmi2);
         goto avx512f_imm8_no_sae;
 
+    case X86EMUL_OPC_EVEX   (0x0f3a, 0x8d): /* top4mxbf8ps $imm8,zmm,zmm,tmm */
+    case X86EMUL_OPC_EVEX_66(0x0f3a, 0x8d): /* top4mxhf8ps $imm8,zmm,zmm,tmm */
+    case X86EMUL_OPC_EVEX_F3(0x0f3a, 0x8d): /* top4mxhbf8ps $imm8,zmm,zmm,tmm 
*/
+    case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x8d): /* top4mxbhf8ps $imm8,zmm,zmm,tmm 
*/
+    case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x8f): /* top4mxbssps $imm8,zmm,zmm,tmm */
+        if ( ea.type != OP_REG )
+            goto unrecognized_insn;
+        generate_exception_if((!mode_64bit() || evex.lr != 2 || evex.opmsk ||
+                               evex.brs || evex.w),
+                              X86_EXC_UD);
+        vcpu_must_have(ace);
+
+        get_fpu(X86EMUL_FPU_zmm_ace);
+        sttilecfg(&mmvalp->tilecfg);
+        generate_exception_if(!tile_valid(modrm_reg, &mmvalp->tilecfg,
+                                          PALETTE(ACE)),
+                              X86_EXC_UD);
+
+        opc = init_evex(stub);
+        opc[0] = b;
+        opc[1] = modrm;
+        opc[2] = imm1;
+        insn_bytes = EVEX_PFX_BYTES + 3;
+        op_bytes = 1; /* fake */
+        break;
+
     case X86EMUL_OPC_EVEX_F3(0x0f3a, 0xc2): /* vcmpsh $imm8,xmm/mem,xmm,k{k} */
         generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD);
         /* fall through */
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -355,7 +355,7 @@ XEN_CPUFEATURE(UC_LOCK_DIS,        13*32
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */
 XEN_CPUFEATURE(MSR_IMM,            14*32+ 5) /*s  RDMSR/WRMSRNS with immediate 
operand */
-XEN_CPUFEATURE(ACE,                14*32+11) /*   AI Compute Extensions */
+XEN_CPUFEATURE(ACE,                14*32+11) /*a  AI Compute Extensions */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */
 XEN_CPUFEATURE(AVX_VNNI_INT8,      15*32+ 4) /*A  AVX-VNNI-INT8 Instructions */