[PATCH v4 24/28] x86/CPUID: enable ACE

[Jan Beulich <jbeulich@xxxxxxxx>]

..., keeping it unavailable to guests of course.

Also include the little bit of XCR0 handling adjustment which is needed.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
v4: New.

--- a/tools/tests/cpu-policy/test-cpu-policy.c
+++ b/tools/tests/cpu-policy/test-cpu-policy.c
@@ -623,6 +623,19 @@ static void test_cpuid_out_of_range_clea
             },
         },
         {
+            .name = "tile palette 2",
+            .nr_markers = 1,
+            .p = {
+                /* First and third subleaves valid as a pair.  Others cleared. 
*/
+                .basic.max_leaf = 0x1d,
+                .feat.ace = 1,
+                .xstate.xcr0_low = XSTATE_FP_SSE | X86_XCR0_TILE_CFG |
+                                   X86_XCR0_TILE_DATA | X86_XCR0_BSR,
+                .tile.raw[0].a = 2,
+                .tile.raw[2].b = 0xc2,
+            },
+        },
+        {
             .name = "extd",
             .nr_markers = 1,
             .p = {
@@ -726,6 +739,15 @@ static void test_cpuid_maximum_leaf_shri
             },
         },
         {
+            .name = "ace v1",
+            .p = {
+                /* Subleaf 2 only with some valid value. */
+                .basic.max_leaf = 0x1d,
+                .tile.raw[0].a = 2,
+                .tile.raw[2].a = 1,
+            },
+        },
+        {
             .name = "tmul",
             .p = {
                 /* Subleaf 0 only with some valid values. */
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -217,7 +217,9 @@ static void recalculate_xstate(struct cp
     if ( p->feat.pku )
         xstates |= X86_XCR0_PKRU;
 
-    if ( p->feat.amx_tile )
+    if ( p->feat.ace )
+        xstates |= X86_XCR0_TILE_CFG | X86_XCR0_TILE_DATA | X86_XCR0_BSR;
+    else if ( p->feat.amx_tile )
         xstates |= X86_XCR0_TILE_CFG | X86_XCR0_TILE_DATA;
 
     if ( p->feat.apx_f )
@@ -262,9 +264,11 @@ static void recalculate_xstate(struct cp
 static void recalculate_tile(struct cpu_policy *p)
 {
     if ( !p->feat.amx_tile )
+        memset(&p->tmul, 0, sizeof(p->tmul));
+
+    if ( !p->feat.amx_tile && !p->feat.ace )
     {
         memset(&p->tile, 0, sizeof(p->tile));
-        memset(&p->tmul, 0, sizeof(p->tmul));
         return;
     }
 
@@ -278,6 +282,14 @@ static void recalculate_tile(struct cpu_
         p->tile.raw[1].d = 0;
     }
 
+    if ( p->tile.max_palette >= 2 )
+    {
+        p->tile.raw[1].a &= 0x000000ff;
+        p->tile.raw[1].b = 0;
+        p->tile.raw[1].c = 0;
+        p->tile.raw[1].d = 0;
+    }
+
     p->tmul.raw[0].a = 0;
     p->tmul.raw[0].b &= 0x00ffffff;
     p->tmul.raw[0].c = 0,
@@ -1245,11 +1257,10 @@ void __init init_dom0_cpuid_policy(struc
          * Default-off features with their own leaves need those leaves
          * re-populated from the max policy.
          */
-        if ( p->feat.amx_tile )
-        {
+        if ( p->feat.amx_tile || p->feat.ace )
             p->tile = max->tile;
+        if ( p->feat.amx_tile )
             p->tmul = max->tmul;
-        }
         if ( p->feat.avx10 )
             p->avx10 = max->avx10;
         if ( p->feat.apx_f )
--- a/xen/arch/x86/include/asm/x86-defns.h
+++ b/xen/arch/x86/include/asm/x86-defns.h
@@ -110,13 +110,14 @@
 #define X86_XCR0_TILE_CFG         (_AC(1, ULL) << 17)
 #define X86_XCR0_TILE_DATA        (_AC(1, ULL) << 18)
 #define X86_XCR0_APX              (_AC(1, ULL) << 19)
+#define X86_XCR0_BSR              (_AC(1, ULL) << 20)
 #define X86_XCR0_LWP              (_AC(1, ULL) << 62)
 
 #define X86_XCR0_STATES                                                 \
     (X86_XCR0_X87 | X86_XCR0_SSE | X86_XCR0_YMM | X86_XCR0_BNDREGS |    \
      X86_XCR0_BNDCSR | X86_XCR0_OPMASK | X86_XCR0_ZMM |                 \
      X86_XCR0_HI_ZMM | X86_XCR0_PKRU | X86_XCR0_TILE_CFG |              \
-     X86_XCR0_TILE_DATA | X86_XCR0_APX |                                \
+     X86_XCR0_TILE_DATA | X86_XCR0_APX | X86_XCR0_BSR |                 \
      X86_XCR0_LWP)
 
 #define X86_XSS_STATES                                                  \
--- a/xen/arch/x86/lib/cpu-policy/cpuid.c
+++ b/xen/arch/x86/lib/cpu-policy/cpuid.c
@@ -409,7 +409,7 @@ void x86_cpu_policy_shrink_max_leaves(st
         p->tile.max_palette = i;
     else
     {
-        ASSERT(!p->feat.amx_tile);
+        ASSERT(!p->feat.amx_tile && !p->feat.ace);
         zero_leaves(p->tile.raw, 0, 0);
     }
     p->basic.raw[0x1d] = p->tile.raw[0];
--- a/xen/arch/x86/lib/cpu-policy/policy.c
+++ b/xen/arch/x86/lib/cpu-policy/policy.c
@@ -25,6 +25,7 @@ int x86_cpu_policies_are_compatible(cons
         FAIL_CPUID(7, 0);
 
     if ( (guest->feat.amx_tile && !guest->tile.max_palette) ||
+         (guest->feat.ace && guest->tile.max_palette < 2) ||
          guest->tile.max_palette > host->tile.max_palette )
         FAIL_CPUID(0x1d, 0);
 
@@ -41,6 +42,10 @@ int x86_cpu_policies_are_compatible(cons
             FAIL_CPUID(0x1d, 1);
     }
 
+    if ( guest->tile.max_palette >= 2 &&
+         guest->tile.ace.version > host->tile.ace.version )
+        FAIL_CPUID(0x1d, 2);
+
     if ( guest->tmul.max_subleaf > host->tmul.max_subleaf ||
          ((guest->feat.amx_int8 || guest->feat.amx_bf16 ||
            guest->feat.amx_fp16 || guest->feat.amx_complex ||
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -1603,7 +1603,8 @@ int x86emul_decode(struct x86_emulate_st
          * environments.
          */
         if ( !mode_64bit() )
-            s->xcr0 &= ~(X86_XCR0_TILE_CFG | X86_XCR0_TILE_DATA | 
X86_XCR0_APX);
+            s->xcr0 &= ~(X86_XCR0_TILE_CFG | X86_XCR0_TILE_DATA | X86_XCR0_APX 
|
+                         X86_XCR0_BSR);
     }
 
     /* Prefix bytes. */
--- a/xen/arch/x86/xstate.c
+++ b/xen/arch/x86/xstate.c
@@ -642,6 +642,10 @@ static bool valid_xcr0(uint64_t xcr0)
     if ( !(xcr0 & X86_XCR0_TILE_CFG) != !(xcr0 & X86_XCR0_TILE_DATA) )
         return false;
 
+    /* BSR requires TILE{CFG,DATA} to also be set. */
+    if ( (xcr0 & X86_XCR0_BSR) && !(xcr0 & X86_XCR0_TILE_CFG) )
+        return false;
+
     return true;
 }
 
@@ -877,7 +881,10 @@ static void __init noinline xstate_check
     if ( cpu_has_xsaves && boot_cpu_has(X86_FEATURE_ARCH_LBR) )
         check_new_xstate(&s, X86_XSS_LBR);
 
-    if ( boot_cpu_has(X86_FEATURE_AMX_TILE) )
+    if ( boot_cpu_has(X86_FEATURE_ACE) )
+        check_new_xstate(&s,
+                         X86_XCR0_TILE_DATA | X86_XCR0_TILE_CFG | 
X86_XCR0_BSR);
+    else if ( boot_cpu_has(X86_FEATURE_AMX_TILE) )
         check_new_xstate(&s, X86_XCR0_TILE_DATA | X86_XCR0_TILE_CFG);
 
     if ( cpu_has_apx_f )
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -355,6 +355,7 @@ XEN_CPUFEATURE(UC_LOCK_DIS,        13*32
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */
 XEN_CPUFEATURE(MSR_IMM,            14*32+ 5) /*s  RDMSR/WRMSRNS with immediate 
operand */
+XEN_CPUFEATURE(ACE,                14*32+11) /*   AI Compute Extensions */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */
 XEN_CPUFEATURE(AVX_VNNI_INT8,      15*32+ 4) /*A  AVX-VNNI-INT8 Instructions */
--- a/xen/include/xen/lib/x86/cpu-policy.h
+++ b/xen/include/xen/lib/x86/cpu-policy.h
@@ -67,7 +67,7 @@ const char *x86_cpuid_vendor_to_str(unsi
 #define CPUID_GUEST_NR_FEAT       (2u + 1)
 #define CPUID_GUEST_NR_TOPO       (1u + 1)
 #define CPUID_GUEST_NR_XSTATE     (62u + 1)
-#define CPUID_GUEST_NR_PALETTE    (1u + 1)
+#define CPUID_GUEST_NR_PALETTE    (2u + 1)
 #define CPUID_GUEST_NR_TMUL       (1u + 1)
 #define CPUID_GUEST_NR_AVX10      (1u + 1)
 #define CPUID_GUEST_NR_APX        (0u + 1)
@@ -286,6 +286,14 @@ struct cpu_policy
                 uint16_t max_rows, :16;
                 uint32_t /* d */:32;
             } palette1;
+
+            /* Palette (subleaf) 2 (ACE). */
+            struct {
+                uint32_t version:8, :24;
+                uint32_t /* b */:32;
+                uint32_t /* c */:32;
+                uint32_t /* d */:32;
+            } ace;
         };
     } tile;
 
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -314,6 +314,8 @@ def crunch_numbers(state):
         # AVX10 discrete features.
         AVX10: [AVX10_BMM, AVX10_V1_AUX, AVX10_V2_AUX],
 
+        AVX10_V2_AUX: [ACE],
+
         # Extensions with VEX/EVEX encodings keyed to a separate feature
         # flag are made dependents of their respective legacy feature.
         PCLMULQDQ: [VPCLMULQDQ],