[PATCH v4 18/28] x86: permit guests to use AMX and XFD

[Jan Beulich <jbeulich@xxxxxxxx>]

These features are marked experimental (for only limited testing having
been done so far) and opt-in for guests.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
v4: AMX-FP16 and AMX-COMPLEX. Re-base.
v3: New.

--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -20,6 +20,7 @@ The format is based on [Keep a Changelog
    - Support for AVX10.2. (Experimental)
    - Support for AVX10-V2-AUX. (Experimental)
    - Support for APX. (Experimental)
+   - Support for AMX and XFD. (Experimental)
 
 ### Removed
  - On Arm:
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -91,6 +91,10 @@ For the Cortex A77 r0p0 - r1p0, see Erra
 
     Status: Experimental
 
+### x86 AMX and XFD
+
+    Status: Experimental
+
 ### IOMMU
 
     Status, AMD IOMMU: Supported
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -182,7 +182,7 @@ XEN_CPUFEATURE(XSAVEOPT,      4*32+ 0) /
 XEN_CPUFEATURE(XSAVEC,        4*32+ 1) /*A  XSAVEC/XRSTORC instructions */
 XEN_CPUFEATURE(XGETBV1,       4*32+ 2) /*A  XGETBV with %ecx=1 */
 XEN_CPUFEATURE(XSAVES,        4*32+ 3) /*S  XSAVES/XRSTORS instructions */
-XEN_CPUFEATURE(XFD,           4*32+ 4) /*   MSR_XFD{,_ERR} (eXtended Feature 
Disable) */
+XEN_CPUFEATURE(XFD,           4*32+ 4) /*a  MSR_XFD{,_ERR} (eXtended Feature 
Disable) */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */
 XEN_CPUFEATURE(FSGSBASE,      5*32+ 0) /*A  {RD,WR}{FS,GS}BASE instructions */
@@ -287,10 +287,10 @@ XEN_CPUFEATURE(TSXLDTRK,      9*32+16) /
 XEN_CPUFEATURE(PCONFIG,       9*32+18) /*   PCONFIG instruction */
 XEN_CPUFEATURE(ARCH_LBR,      9*32+19) /*   Architectural Last Branch Record */
 XEN_CPUFEATURE(CET_IBT,       9*32+20) /*   CET - Indirect Branch Tracking */
-XEN_CPUFEATURE(AMX_BF16,      9*32+22) /*   AMX BFloat16 instruction */
+XEN_CPUFEATURE(AMX_BF16,      9*32+22) /*a  AMX BFloat16 instruction */
 XEN_CPUFEATURE(AVX512_FP16,   9*32+23) /*A  AVX512 FP16 instructions */
-XEN_CPUFEATURE(AMX_TILE,      9*32+24) /*   AMX Tile architecture */
-XEN_CPUFEATURE(AMX_INT8,      9*32+25) /*   AMX 8-bit integer instructions */
+XEN_CPUFEATURE(AMX_TILE,      9*32+24) /*a  AMX Tile architecture */
+XEN_CPUFEATURE(AMX_INT8,      9*32+25) /*a  AMX 8-bit integer instructions */
 XEN_CPUFEATURE(IBRSB,         9*32+26) /*A  IBRS and IBPB support (used by 
Intel) */
 XEN_CPUFEATURE(STIBP,         9*32+27) /*A  STIBP */
 XEN_CPUFEATURE(L1D_FLUSH,     9*32+28) /*S  MSR_FLUSH_CMD and L1D flush. */
@@ -314,7 +314,7 @@ XEN_CPUFEATURE(FRED,         10*32+17) /
 XEN_CPUFEATURE(LKGS,         10*32+18) /*   Load Kernel GS instruction */
 XEN_CPUFEATURE(WRMSRNS,      10*32+19) /*S  WRMSR Non-Serialising */
 XEN_CPUFEATURE(NMI_SRC,      10*32+20) /*   NMI-Source Reporting */
-XEN_CPUFEATURE(AMX_FP16,     10*32+21) /*   AMX FP16 instruction */
+XEN_CPUFEATURE(AMX_FP16,     10*32+21) /*a  AMX FP16 instruction */
 XEN_CPUFEATURE(AVX_IFMA,     10*32+23) /*A  AVX-IFMA Instructions */
 XEN_CPUFEATURE(LAM,          10*32+26) /*   Linear Address Masking */
 XEN_CPUFEATURE(MSRLIST,      10*32+27) /*s  {RD,WR}MSRLIST instructions */
@@ -359,7 +359,7 @@ XEN_CPUFEATURE(MSR_IMM,            14*32
 /* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */
 XEN_CPUFEATURE(AVX_VNNI_INT8,      15*32+ 4) /*A  AVX-VNNI-INT8 Instructions */
 XEN_CPUFEATURE(AVX_NE_CONVERT,     15*32+ 5) /*A  AVX-NE-CONVERT Instructions 
*/
-XEN_CPUFEATURE(AMX_COMPLEX,        15*32+ 8) /*   AMX Complex Instructions */
+XEN_CPUFEATURE(AMX_COMPLEX,        15*32+ 8) /*a  AMX Complex Instructions */
 XEN_CPUFEATURE(AVX_VNNI_INT16,     15*32+10) /*A  AVX-VNNI-INT16 Instructions 
*/
 XEN_CPUFEATURE(UTMR,               15*32+13) /*   User Timer */
 XEN_CPUFEATURE(PREFETCHI,          15*32+14) /*A  PREFETCHIT{0,1} Instructions 
*/