[PATCH v4 14/28] x86emul: support tile multiplication insns

[Jan Beulich <jbeulich@xxxxxxxx>]

Since these don't allow for memory operands, the main thing to do here
is to check the large set of #UD conditions.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
v4: AMX-FP16 and AMX-COMPLEX. Comment out yet another redundant #UD
    check. Drop (wrong) use of "unimplemented_insn". Use X86_EXC_*.
    Re-base.
v3: New.

--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -1363,6 +1363,14 @@ static const struct vex {
     { { 0x58 }, 2, T, R, pfx_66, W0, Ln }, /* vpbroadcastd */
     { { 0x59 }, 2, T, R, pfx_66, W0, Ln }, /* vpbroadcastq */
     { { 0x5a }, 2, F, R, pfx_66, W0, L1 }, /* vbroadcasti128 */
+    { { 0x5c, 0xc0 }, 2, F, N, pfx_f3, W0, L0 }, /* tdpbf16ps */
+    { { 0x5c, 0xc0 }, 2, F, N, pfx_f2, W0, L0 }, /* tdpfp16ps */
+    { { 0x5e, 0xc0 }, 2, F, N, pfx_no, W0, L0 }, /* tdpbuud */
+    { { 0x5e, 0xc0 }, 2, F, N, pfx_66, W0, L0 }, /* tdpbusd */
+    { { 0x5e, 0xc0 }, 2, F, N, pfx_f3, W0, L0 }, /* tdpbsud */
+    { { 0x5e, 0xc0 }, 2, F, N, pfx_f2, W0, L0 }, /* tdpbssd */
+    { { 0x6c, 0xc0 }, 2, F, N, pfx_no, W0, L0 }, /* tcmmrlfp16ps */
+    { { 0x6c, 0xc0 }, 2, F, N, pfx_66, W0, L0 }, /* tcmmimfp16ps */
     { { 0x72 }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtneps2bf16 */
     { { 0x78 }, 2, T, R, pfx_66, W0, Ln }, /* vpbroadcastb */
     { { 0x79 }, 2, T, R, pfx_66, W0, Ln }, /* vpbroadcastw */
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -377,11 +377,14 @@ static const struct ext0f38_table {
     [0x59] = { .simd_size = simd_other, .two_op = 1, .d8s = 3 },
     [0x5a] = { .simd_size = simd_128, .two_op = 1, .d8s = 4 },
     [0x5b] = { .simd_size = simd_256, .two_op = 1, .d8s = d8s_vl_by_2 },
+    [0x5c] = { .simd_size = simd_other },
+    [0x5e] = { .simd_size = simd_other },
     [0x62] = { .simd_size = simd_packed_int, .two_op = 1, .d8s = d8s_bw },
     [0x63] = { .simd_size = simd_packed_int, .to_mem = 1, .two_op = 1, .d8s = 
d8s_bw },
     [0x64 ... 0x66] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
     [0x67] = { .simd_size = simd_other, .d8s = d8s_vl },
     [0x68] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
+    [0x6c] = { .simd_size = simd_other },
     [0x70 ... 0x73] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
     [0x74] = { .simd_size = simd_other, .d8s = d8s_vl },
     [0x75 ... 0x76] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
--- a/xen/arch/x86/x86_emulate/private.h
+++ b/xen/arch/x86/x86_emulate/private.h
@@ -606,7 +606,9 @@ amd_like(const struct x86_emulate_ctxt *
 #define vcpu_has_avx512_vp2intersect() (ctxt->cpuid->feat.avx512_vp2intersect)
 #define vcpu_has_serialize()   (ctxt->cpuid->feat.serialize)
 #define vcpu_has_tsxldtrk()    (ctxt->cpuid->feat.tsxldtrk)
+#define vcpu_has_amx_bf16()    (ctxt->cpuid->feat.amx_bf16)
 #define vcpu_has_amx_tile()    (ctxt->cpuid->feat.amx_tile)
+#define vcpu_has_amx_int8()    (ctxt->cpuid->feat.amx_int8)
 #define vcpu_has_sha512()      (ctxt->cpuid->feat.sha512)
 #define vcpu_has_sm3()         (ctxt->cpuid->feat.sm3)
 #define vcpu_has_sm4()         (ctxt->cpuid->feat.sm4)
@@ -614,12 +616,14 @@ amd_like(const struct x86_emulate_ctxt *
 #define vcpu_has_cmpccxadd()   (ctxt->cpuid->feat.cmpccxadd)
 #define vcpu_has_lkgs()        (ctxt->cpuid->feat.lkgs)
 #define vcpu_has_wrmsrns()     (ctxt->cpuid->feat.wrmsrns)
+#define vcpu_has_amx_fp16()    (ctxt->cpuid->feat.amx_fp16)
 #define vcpu_has_avx_ifma()    (ctxt->cpuid->feat.avx_ifma)
 #define vcpu_has_msrlist()     (ctxt->cpuid->feat.msrlist)
 #define vcpu_has_movrs()       (ctxt->cpuid->feat.movrs)
 #define vcpu_has_msr_imm()     (ctxt->cpuid->feat.msr_imm)
 #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8)
 #define vcpu_has_avx_ne_convert() (ctxt->cpuid->feat.avx_ne_convert)
+#define vcpu_has_amx_complex() (ctxt->cpuid->feat.amx_complex)
 #define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16)
 #define vcpu_has_user_msr()    (ctxt->cpuid->feat.user_msr)
 
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -6976,6 +6976,71 @@ x86_emulate(
         generate_exception_if(ea.type != OP_MEM || !vex.l || vex.w, 
X86_EXC_UD);
         goto simd_0f_avx2;
 
+    case X86EMUL_OPC_VEX_F3(0x0f38, 0x5c): /* tdpbf16ps tmm,tmm,tmm */
+    case X86EMUL_OPC_VEX_F2(0x0f38, 0x5c): /* tdpfp16ps tmm,tmm,tmm */
+    case X86EMUL_OPC_VEX   (0x0f38, 0x5e): /* tdpbuud tmm,tmm,tmm */
+    case X86EMUL_OPC_VEX_66(0x0f38, 0x5e): /* tdpbusd tmm,tmm,tmm */
+    case X86EMUL_OPC_VEX_F3(0x0f38, 0x5e): /* tdpbsud tmm,tmm,tmm */
+    case X86EMUL_OPC_VEX_F2(0x0f38, 0x5e): /* tdpbssd tmm,tmm,tmm */
+    case X86EMUL_OPC_VEX   (0x0f38, 0x6c): /* tcmmrlfp16ps tmm,tmm,tmm */
+    case X86EMUL_OPC_VEX_66(0x0f38, 0x6c): /* tcmmimfp16ps tmm,tmm,tmm */
+    {
+        unsigned int vreg = vex.reg ^ 0xf;
+
+        if ( ea.type != OP_REG )
+            goto unrecognized_insn;
+        generate_exception_if(!mode_64bit() || vex.l || vex.w, X86_EXC_UD);
+        if ( b == 0x5e )
+            vcpu_must_have(amx_int8);
+        else if ( b == 0x6c )
+            vcpu_must_have(amx_complex);
+        else if ( vex.pfx != vex_f2 )
+            vcpu_must_have(amx_bf16);
+        else
+            vcpu_must_have(amx_fp16);
+        generate_exception_if(modrm_reg == modrm_rm, X86_EXC_UD);
+        generate_exception_if(modrm_reg == vreg, X86_EXC_UD);
+        generate_exception_if(modrm_rm == vreg, X86_EXC_UD);
+
+        get_fpu(X86EMUL_FPU_tile);
+        sttilecfg(&mmvalp->tilecfg);
+
+        /* accum: modrm_reg */
+        generate_exception_if(!tile_valid(modrm_reg, &mmvalp->tilecfg,
+                                          PALETTE(AMX)),
+                              X86_EXC_UD);
+        generate_exception_if(mmvalp->tilecfg.colsb[modrm_reg] & 3,
+                              X86_EXC_UD);
+        /* src1: modrm_rm */
+        generate_exception_if(!tile_valid(modrm_rm, &mmvalp->tilecfg,
+                                          PALETTE(AMX)),
+                              X86_EXC_UD);
+        /*
+         * These are redundant with the checks just below.
+        generate_exception_if(mmvalp->tilecfg.colsb[modrm_rm] & 3,
+                              X86_EXC_UD);
+         * src2: vreg
+        generate_exception_if(!tile_valid(vreg, &mmvalp->tilecfg, 
PALETTE(AMX)),
+                              X86_EXC_UD);
+        generate_exception_if(mmvalp->tilecfg.colsb[vreg] & 3, X86_EXC_UD);
+         */
+
+        generate_exception_if(mmvalp->tilecfg.rows[modrm_reg] !=
+                              mmvalp->tilecfg.rows[modrm_rm], X86_EXC_UD);
+        generate_exception_if(mmvalp->tilecfg.colsb[modrm_reg] !=
+                              mmvalp->tilecfg.colsb[vreg], X86_EXC_UD);
+        generate_exception_if(mmvalp->tilecfg.colsb[modrm_rm] !=
+                              mmvalp->tilecfg.rows[vreg] * 4, X86_EXC_UD);
+
+        generate_exception_if(mmvalp->tilecfg.colsb[vreg] >
+                              cp->tmul.maxn, X86_EXC_UD);
+        generate_exception_if(mmvalp->tilecfg.rows[vreg] >
+                              cp->tmul.maxk, X86_EXC_UD);
+
+        op_bytes = 1; /* fake */
+        goto simd_0f_common;
+    }
+
     case X86EMUL_OPC_EVEX_66(0x0f38, 0x62): /* vpexpand{b,w} 
[xyz]mm/mem,[xyz]mm{k} */
     case X86EMUL_OPC_EVEX_66(0x0f38, 0x63): /* vpcompress{b,w} 
[xyz]mm,[xyz]mm/mem{k} */
         visa_check(_vbmi2);