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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v4 03/28] x86/xstate: replace xsave_cntxt_size and drop XCNTXT_MASK
XCNTXT_MASK is effectively embedded in recalculate_xstate(), and
xsave_cntxt_size is redundant with the host CPUID policy's xstate.max_size
field.
Use the host CPUID policy as input (requiring it to be calculated early
enough), thus allowing e.g. "cpuid=no-avx512f" to also result in avoiding
allocation of space for ZMM and mask register state.
Also drop a stale part of an adjacent comment.
Further where respective code is being touched anyway, also replace
XSTATE_CPUID by 0xd.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
Andrew voiced objection to the use of the host policy here, yet without
indicating what else to use instead. Perhaps that concern is taken care of
by "x86/cpu-policy: set up host policy earlier"?
---
v4: Re-base.
--- a/xen/arch/x86/include/asm/xstate.h
+++ b/xen/arch/x86/include/asm/xstate.h
@@ -31,10 +31,6 @@ extern uint32_t mxcsr_mask;
#define XSTATE_AREA_MIN_SIZE (FXSAVE_SIZE + XSAVE_HDR_SIZE)
#define XSTATE_FP_SSE (X86_XCR0_X87 | X86_XCR0_SSE)
-#define XCNTXT_MASK (X86_XCR0_X87 | X86_XCR0_SSE | X86_XCR0_YMM | \
- X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM | \
- X86_XCR0_BNDREGS | X86_XCR0_BNDCSR | X86_XCR0_PKRU | \
- X86_XCR0_TILE_CFG | X86_XCR0_TILE_DATA | X86_XCR0_APX)
#define XSTATE_ALL (~(1ULL << 63))
#define XSTATE_XSAVES_ONLY 0
--- a/xen/arch/x86/xstate.c
+++ b/xen/arch/x86/xstate.c
@@ -21,9 +21,10 @@
/*
* Maximum size (in byte) of the XSAVE/XRSTOR save area required by all
* the supported and enabled features on the processor, including the
- * XSAVE.HEADER. We only enable XCNTXT_MASK that we have known.
+ * XSAVE.HEADER. We only enable cpu_policy_xcr0_max(&host_cpu_policy).
+ * Note that this identifier should not be usable as an lvalue.
*/
-static u32 __read_mostly xsave_cntxt_size;
+#define xsave_cntxt_size (host_cpu_policy.xstate.max_size | 0)
/* A 64-bit bitmask of the XSAVE/XRSTOR features supported by processor. */
u64 __read_mostly xfeature_mask;
@@ -902,23 +903,31 @@ void xstate_init(struct cpuinfo_x86 *c)
if ( !cpu_has_xsave )
return;
- if ( (bsp && !use_xsave) ||
- boot_cpu_data.cpuid_level < XSTATE_CPUID )
+ if ( (bsp && !use_xsave) || c->cpuid_level < 0xd )
{
BUG_ON(!bsp);
setup_clear_cpu_cap(X86_FEATURE_XSAVE);
return;
}
- cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
- feature_mask = (((u64)edx << 32) | eax) & XCNTXT_MASK;
- BUG_ON(!valid_xcr0(feature_mask));
- BUG_ON(!(feature_mask & X86_XCR0_SSE));
+ if ( bsp )
+ {
+ feature_mask = cpu_policy_xcr0_max(&host_cpu_policy);
+ BUG_ON(!valid_xcr0(feature_mask));
+ BUG_ON(!(feature_mask & X86_XCR0_SSE));
- /*
- * Set CR4_OSXSAVE and run "cpuid" to get xsave_cntxt_size.
- */
- set_in_cr4(X86_CR4_OSXSAVE);
+ xfeature_mask = feature_mask;
+
+ /* xsave_cntxt_size is the max size required by enabled features. */
+ printk("xstate: size: %#x and states: %#"PRIx64"\n",
+ xsave_cntxt_size, feature_mask);
+
+ set_in_cr4(X86_CR4_OSXSAVE);
+ }
+
+ cpuid_count(0xd, 0, &eax, &ebx, &ecx, &edx);
+ feature_mask = (((uint64_t)edx << 32) | eax) & xfeature_mask;
+ BUG_ON(xfeature_mask != feature_mask);
/*
* Zap the cached values to make set_xcr0() and set_msr_xss() really write
@@ -933,22 +942,7 @@ void xstate_init(struct cpuinfo_x86 *c)
set_msr_xss(0);
}
- if ( bsp )
- {
- xfeature_mask = feature_mask;
- /*
- * xsave_cntxt_size is the max size required by enabled features.
- * We know FP/SSE and YMM about eax, and nothing about edx at present.
- */
- xsave_cntxt_size = cpuid_count_ebx(0xd, 0);
- printk("xstate: size: %#x and states: %#"PRIx64"\n",
- xsave_cntxt_size, xfeature_mask);
- }
- else
- {
- BUG_ON(xfeature_mask != feature_mask);
- BUG_ON(xsave_cntxt_size != cpuid_count_ebx(0xd, 0));
- }
+ BUG_ON(xsave_cntxt_size != cpuid_count_ebx(0xd, 0));
if ( setup_xstate_features(bsp) && bsp )
BUG();
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