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[PATCH 15/30] x86emul: support APX EVEX-encoded shift/rotate insns

  • To: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Wed, 11 Nov 2026 15:26:35 +0100
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  • Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Teddy Astie <teddy.astie@xxxxxxxxxx>, Roger Pau Monné <roger@xxxxxxxxxxxxxx>
  • Delivery-date: Wed, 11 Nov 2026 14:26:42 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
With generic logic having been put in place this is largely mechanical
addition of new table entries / case labels. Pre-existing testcases are
once again cloned into EVEX counterpart forms.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -931,6 +931,86 @@ static const struct test apx_f[] = {
     INSN(orw,       66, map4, 0b,    el,    w, no),
     INSNX(orw,      66, map4, 81, 1, el,    w, no),
     INSNX(orw,      66, map4, 83, 1, el,    w, no),
+    INSNX(rcl,        , map4, c1, 2, el,   dq, no),
+    INSNX(rcl,        , map4, d1, 2, el,   dq, no),
+    INSNX(rcl,        , map4, d3, 2, el,   dq, no),
+    INSNX(rclb,       , map4, c0, 2, el,    b, no),
+    INSNX(rclb,       , map4, d0, 2, el,    b, no),
+    INSNX(rclb,       , map4, d2, 2, el,    b, no),
+    INSNX(rclw,     66, map4, c1, 2, el,    w, no),
+    INSNX(rclw,     66, map4, d1, 2, el,    w, no),
+    INSNX(rclw,     66, map4, d3, 2, el,    w, no),
+    INSNX(rcr,        , map4, c1, 3, el,   dq, no),
+    INSNX(rcr,        , map4, d1, 3, el,   dq, no),
+    INSNX(rcr,        , map4, d3, 3, el,   dq, no),
+    INSNX(rcrb,       , map4, c0, 3, el,    b, no),
+    INSNX(rcrb,       , map4, d0, 3, el,    b, no),
+    INSNX(rcrb,       , map4, d2, 3, el,    b, no),
+    INSNX(rcrw,     66, map4, c1, 3, el,    w, no),
+    INSNX(rcrw,     66, map4, d1, 3, el,    w, no),
+    INSNX(rcrw,     66, map4, d3, 3, el,    w, no),
+    INSNX(rol,        , map4, c1, 0, el,   dq, no),
+    INSNX(rol,        , map4, d1, 0, el,   dq, no),
+    INSNX(rol,        , map4, d3, 0, el,   dq, no),
+    INSNX(rolb,       , map4, c0, 0, el,    b, no),
+    INSNX(rolb,       , map4, d0, 0, el,    b, no),
+    INSNX(rolb,       , map4, d2, 0, el,    b, no),
+    INSNX(rolw,     66, map4, c1, 0, el,    w, no),
+    INSNX(rolw,     66, map4, d1, 0, el,    w, no),
+    INSNX(rolw,     66, map4, d3, 0, el,    w, no),
+    INSNX(ror,        , map4, c1, 1, el,   dq, no),
+    INSNX(ror,        , map4, d1, 1, el,   dq, no),
+    INSNX(ror,        , map4, d3, 1, el,   dq, no),
+    INSNX(rorb,       , map4, c0, 1, el,    b, no),
+    INSNX(rorb,       , map4, d0, 1, el,    b, no),
+    INSNX(rorb,       , map4, d2, 1, el,    b, no),
+    INSNX(rorw,     66, map4, c1, 1, el,    w, no),
+    INSNX(rorw,     66, map4, d1, 1, el,    w, no),
+    INSNX(rorw,     66, map4, d3, 1, el,    w, no),
+    INSNX(shl,        , map4, c1, 4, el,   dq, no),
+    INSNX(shl,        , map4, d1, 4, el,   dq, no),
+    INSNX(shl,        , map4, d3, 4, el,   dq, no),
+    INSNX(shlb,       , map4, c0, 4, el,    b, no),
+    INSNX(shlb,       , map4, d0, 4, el,    b, no),
+    INSNX(shlb,       , map4, d2, 4, el,    b, no),
+    INSN(shld,        , map4, 24,    el,   dq, no),
+    INSN(shld,        , map4, a5,    el,   dq, no),
+    INSN(shldw,     66, map4, 24,    el,    w, no),
+    INSN(shldw,     66, map4, a5,    el,    w, no),
+    INSNX(shlw,     66, map4, c1, 4, el,    w, no),
+    INSNX(shlw,     66, map4, d1, 4, el,    w, no),
+    INSNX(shlw,     66, map4, d3, 4, el,    w, no),
+    INSNX(shr,        , map4, c1, 5, el,   dq, no),
+    INSNX(shr,        , map4, d1, 5, el,   dq, no),
+    INSNX(shr,        , map4, d3, 5, el,   dq, no),
+    INSNX(shrb,       , map4, c0, 5, el,    b, no),
+    INSNX(shrb,       , map4, d0, 5, el,    b, no),
+    INSNX(shrb,       , map4, d2, 5, el,    b, no),
+    INSN(shrd,        , map4, 2c,    el,   dq, no),
+    INSN(shrd,        , map4, ad,    el,   dq, no),
+    INSN(shrdw,     66, map4, 2c,    el,    w, no),
+    INSN(shrdw,     66, map4, ad,    el,    w, no),
+    INSNX(shrw,     66, map4, c1, 5, el,    w, no),
+    INSNX(shrw,     66, map4, d1, 5, el,    w, no),
+    INSNX(shrw,     66, map4, d3, 5, el,    w, no),
+    INSNX(sal,        , map4, c1, 6, el,   dq, no),
+    INSNX(sal,        , map4, d1, 6, el,   dq, no),
+    INSNX(sal,        , map4, d3, 6, el,   dq, no),
+    INSNX(salb,       , map4, c0, 6, el,    b, no),
+    INSNX(salb,       , map4, d0, 6, el,    b, no),
+    INSNX(salb,       , map4, d2, 6, el,    b, no),
+    INSNX(salw,     66, map4, c1, 6, el,    w, no),
+    INSNX(salw,     66, map4, d1, 6, el,    w, no),
+    INSNX(salw,     66, map4, d3, 6, el,    w, no),
+    INSNX(sar,        , map4, c1, 7, el,   dq, no),
+    INSNX(sar,        , map4, d1, 7, el,   dq, no),
+    INSNX(sar,        , map4, d3, 7, el,   dq, no),
+    INSNX(sarb,       , map4, c0, 7, el,    b, no),
+    INSNX(sarb,       , map4, d0, 7, el,    b, no),
+    INSNX(sarb,       , map4, d2, 7, el,    b, no),
+    INSNX(sarw,     66, map4, c1, 7, el,    w, no),
+    INSNX(sarw,     66, map4, d1, 7, el,    w, no),
+    INSNX(sarw,     66, map4, d3, 7, el,    w, no),
     INSN(sbb,         , map4, 19,    el,   dq, no),
     INSN(sbb,         , map4, 1b,    el,   dq, no),
     INSNX(sbb,        , map4, 81, 3, el,   dq, no),
@@ -993,6 +1073,10 @@ static const uint16_t imm0f[16] = {
  * when operand size is 16-bit.
  */
 static const uint8_t immM4[256] = {
+    [0x24] = 1,
+    [0x2c] = 1,
+    [0xc0] = 1,
+    [0xc1] = 1,
     [0x80] = 1,
     [0x81] = 4,
     [0x83] = 1,
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -2161,12 +2161,16 @@ static const struct evex {
     { { 0x22 }, 2, T, R, pfx_no, WIG, L0, ND }, /* and */
     { { 0x23 }, 2, T, R, pfx_no, Wn, L0, ND }, /* and */
     { { 0x23 }, 2, T, R, pfx_66, Wn, L0, ND }, /* and */
+    { { 0x24 }, 3, T, W, pfx_no, Wn, L0, ND }, /* shld */
+    { { 0x24 }, 3, T, W, pfx_66, Wn, L0, ND }, /* shld */
     { { 0x28 }, 2, T, W, pfx_no, WIG, L0, ND }, /* sub */
     { { 0x29 }, 2, T, W, pfx_no, Wn, L0, ND }, /* sub */
     { { 0x29 }, 2, T, W, pfx_66, Wn, L0, ND }, /* sub */
     { { 0x2a }, 2, T, R, pfx_no, WIG, L0, ND }, /* sub */
     { { 0x2b }, 2, T, R, pfx_no, Wn, L0, ND }, /* sub */
     { { 0x2b }, 2, T, R, pfx_66, Wn, L0, ND }, /* sub */
+    { { 0x2c }, 3, T, W, pfx_no, Wn, L0, ND }, /* shrd */
+    { { 0x2c }, 3, T, W, pfx_66, Wn, L0, ND }, /* shrd */
     { { 0x30 }, 2, T, W, pfx_no, WIG, L0, ND }, /* xor */
     { { 0x31 }, 2, T, W, pfx_no, Wn, L0, ND }, /* xor */
     { { 0x31 }, 2, T, W, pfx_66, Wn, L0, ND }, /* xor */
@@ -2215,6 +2219,82 @@ static const struct evex {
     { { 0x83, 0x28 }, 3, T, W, pfx_66, Wn, L0, ND }, /* sub */
     { { 0x83, 0x30 }, 3, T, W, pfx_no, Wn, L0, ND }, /* xor */
     { { 0x83, 0x30 }, 3, T, W, pfx_66, Wn, L0, ND }, /* xor */
+    { { 0xa5 }, 2, T, W, pfx_no, Wn, L0, ND }, /* shld */
+    { { 0xa5 }, 2, T, W, pfx_66, Wn, L0, ND }, /* shld */
+    { { 0xad }, 2, T, W, pfx_no, Wn, L0, ND }, /* shrd */
+    { { 0xad }, 2, T, W, pfx_66, Wn, L0, ND }, /* shrd */
+    { { 0xc0, 0x00 }, 3, T, W, pfx_no, WIG, L0, ND }, /* rol */
+    { { 0xc0, 0x08 }, 3, T, W, pfx_no, WIG, L0, ND }, /* ror */
+    { { 0xc0, 0x10 }, 3, T, W, pfx_no, WIG, L0, ND }, /* rcl */
+    { { 0xc0, 0x18 }, 3, T, W, pfx_no, WIG, L0, ND }, /* rcr */
+    { { 0xc0, 0x20 }, 3, T, W, pfx_no, WIG, L0, ND }, /* shl */
+    { { 0xc0, 0x28 }, 3, T, W, pfx_no, WIG, L0, ND }, /* shr */
+    { { 0xc0, 0x30 }, 3, T, W, pfx_no, WIG, L0, ND }, /* sal */
+    { { 0xc0, 0x38 }, 3, T, W, pfx_no, WIG, L0, ND }, /* sar */
+    { { 0xc1, 0x00 }, 3, T, W, pfx_no, Wn, L0, ND }, /* rol */
+    { { 0xc1, 0x00 }, 3, T, W, pfx_66, Wn, L0, ND }, /* rol */
+    { { 0xc1, 0x08 }, 3, T, W, pfx_no, Wn, L0, ND }, /* ror */
+    { { 0xc1, 0x08 }, 3, T, W, pfx_66, Wn, L0, ND }, /* ror */
+    { { 0xc1, 0x10 }, 3, T, W, pfx_no, Wn, L0, ND }, /* rcl */
+    { { 0xc1, 0x10 }, 3, T, W, pfx_66, Wn, L0, ND }, /* rcl */
+    { { 0xc1, 0x18 }, 3, T, W, pfx_no, Wn, L0, ND }, /* rcr */
+    { { 0xc1, 0x18 }, 3, T, W, pfx_66, Wn, L0, ND }, /* rcr */
+    { { 0xc1, 0x20 }, 3, T, W, pfx_no, Wn, L0, ND }, /* shl */
+    { { 0xc1, 0x20 }, 3, T, W, pfx_66, Wn, L0, ND }, /* shl */
+    { { 0xc1, 0x28 }, 3, T, W, pfx_no, Wn, L0, ND }, /* shr */
+    { { 0xc1, 0x28 }, 3, T, W, pfx_66, Wn, L0, ND }, /* shr */
+    { { 0xc1, 0x30 }, 3, T, W, pfx_no, Wn, L0, ND }, /* sal */
+    { { 0xc1, 0x30 }, 3, T, W, pfx_66, Wn, L0, ND }, /* sal */
+    { { 0xc1, 0x38 }, 3, T, W, pfx_no, Wn, L0, ND }, /* sar */
+    { { 0xc1, 0x38 }, 3, T, W, pfx_66, Wn, L0, ND }, /* sar */
+    { { 0xd0, 0x00 }, 2, T, W, pfx_no, WIG, L0, ND }, /* rol */
+    { { 0xd0, 0x08 }, 2, T, W, pfx_no, WIG, L0, ND }, /* ror */
+    { { 0xd0, 0x10 }, 2, T, W, pfx_no, WIG, L0, ND }, /* rcl */
+    { { 0xd0, 0x18 }, 2, T, W, pfx_no, WIG, L0, ND }, /* rcr */
+    { { 0xd0, 0x20 }, 2, T, W, pfx_no, WIG, L0, ND }, /* shl */
+    { { 0xd0, 0x28 }, 2, T, W, pfx_no, WIG, L0, ND }, /* shr */
+    { { 0xd0, 0x30 }, 2, T, W, pfx_no, WIG, L0, ND }, /* sal */
+    { { 0xd0, 0x38 }, 2, T, W, pfx_no, WIG, L0, ND }, /* sar */
+    { { 0xd1, 0x00 }, 2, T, W, pfx_no, Wn, L0, ND }, /* rol */
+    { { 0xd1, 0x00 }, 2, T, W, pfx_66, Wn, L0, ND }, /* rol */
+    { { 0xd1, 0x08 }, 2, T, W, pfx_no, Wn, L0, ND }, /* ror */
+    { { 0xd1, 0x08 }, 2, T, W, pfx_66, Wn, L0, ND }, /* ror */
+    { { 0xd1, 0x10 }, 2, T, W, pfx_no, Wn, L0, ND }, /* rcl */
+    { { 0xd1, 0x10 }, 2, T, W, pfx_66, Wn, L0, ND }, /* rcl */
+    { { 0xd1, 0x18 }, 2, T, W, pfx_no, Wn, L0, ND }, /* rcr */
+    { { 0xd1, 0x18 }, 2, T, W, pfx_66, Wn, L0, ND }, /* rcr */
+    { { 0xd1, 0x20 }, 2, T, W, pfx_no, Wn, L0, ND }, /* shl */
+    { { 0xd1, 0x20 }, 2, T, W, pfx_66, Wn, L0, ND }, /* shl */
+    { { 0xd1, 0x28 }, 2, T, W, pfx_no, Wn, L0, ND }, /* shr */
+    { { 0xd1, 0x28 }, 2, T, W, pfx_66, Wn, L0, ND }, /* shr */
+    { { 0xd1, 0x30 }, 2, T, W, pfx_no, Wn, L0, ND }, /* sal */
+    { { 0xd1, 0x30 }, 2, T, W, pfx_66, Wn, L0, ND }, /* sal */
+    { { 0xd1, 0x38 }, 2, T, W, pfx_no, Wn, L0, ND }, /* sar */
+    { { 0xd1, 0x38 }, 2, T, W, pfx_66, Wn, L0, ND }, /* sar */
+    { { 0xd2, 0x00 }, 2, T, W, pfx_no, WIG, L0, ND }, /* rol */
+    { { 0xd2, 0x08 }, 2, T, W, pfx_no, WIG, L0, ND }, /* ror */
+    { { 0xd2, 0x10 }, 2, T, W, pfx_no, WIG, L0, ND }, /* rcl */
+    { { 0xd2, 0x18 }, 2, T, W, pfx_no, WIG, L0, ND }, /* rcr */
+    { { 0xd2, 0x20 }, 2, T, W, pfx_no, WIG, L0, ND }, /* shl */
+    { { 0xd2, 0x28 }, 2, T, W, pfx_no, WIG, L0, ND }, /* shr */
+    { { 0xd2, 0x30 }, 2, T, W, pfx_no, WIG, L0, ND }, /* sal */
+    { { 0xd2, 0x38 }, 2, T, W, pfx_no, WIG, L0, ND }, /* sar */
+    { { 0xd3, 0x00 }, 2, T, W, pfx_no, Wn, L0, ND }, /* rol */
+    { { 0xd3, 0x00 }, 2, T, W, pfx_66, Wn, L0, ND }, /* rol */
+    { { 0xd3, 0x08 }, 2, T, W, pfx_no, Wn, L0, ND }, /* ror */
+    { { 0xd3, 0x08 }, 2, T, W, pfx_66, Wn, L0, ND }, /* ror */
+    { { 0xd3, 0x10 }, 2, T, W, pfx_no, Wn, L0, ND }, /* rcl */
+    { { 0xd3, 0x10 }, 2, T, W, pfx_66, Wn, L0, ND }, /* rcl */
+    { { 0xd3, 0x18 }, 2, T, W, pfx_no, Wn, L0, ND }, /* rcr */
+    { { 0xd3, 0x18 }, 2, T, W, pfx_66, Wn, L0, ND }, /* rcr */
+    { { 0xd3, 0x20 }, 2, T, W, pfx_no, Wn, L0, ND }, /* shl */
+    { { 0xd3, 0x20 }, 2, T, W, pfx_66, Wn, L0, ND }, /* shl */
+    { { 0xd3, 0x28 }, 2, T, W, pfx_no, Wn, L0, ND }, /* shr */
+    { { 0xd3, 0x28 }, 2, T, W, pfx_66, Wn, L0, ND }, /* shr */
+    { { 0xd3, 0x30 }, 2, T, W, pfx_no, Wn, L0, ND }, /* sal */
+    { { 0xd3, 0x30 }, 2, T, W, pfx_66, Wn, L0, ND }, /* sal */
+    { { 0xd3, 0x38 }, 2, T, W, pfx_no, Wn, L0, ND }, /* sar */
+    { { 0xd3, 0x38 }, 2, T, W, pfx_66, Wn, L0, ND }, /* sar */
     { { 0xf6, 0x10 }, 2, T, W, pfx_no, WIG, L0, ND }, /* not */
     { { 0xf6, 0x18 }, 2, T, W, pfx_no, WIG, L0, ND }, /* neg */
     { { 0xf6, 0x20 }, 2, T, R, pfx_no, WIG, L0 }, /* mul */
--- a/tools/tests/x86_emulator/test_x86_emulator.c
+++ b/tools/tests/x86_emulator/test_x86_emulator.c
@@ -1474,6 +1474,66 @@ int main(int argc, char **argv)
             goto fail;
         printf("okay\n");
 
+        printf("%-40s", "Testing rcl $2,(%rdi),%edi...");
+        instr[2] = 0x44; instr[4] = 0xc1; instr[5] = 0x17; instr[6] = 0x02;
+        *res        = 0x2233445f;
+        regs.eflags = EFLAGS_ALWAYS_SET | X86_EFLAGS_CF;
+        regs.rip    = (unsigned long)&instr[0];
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( (rc != X86EMUL_OKAY) ||
+             (regs.rdi != ((0x2233445fU << 2) | 2)) ||
+             (*res != 0x2233445f) ||
+             ((regs.eflags & (EFLAGS_MASK & ~X86_EFLAGS_OF))
+              != EFLAGS_ALWAYS_SET) ||
+             (regs.rip != (unsigned long)&instr[7]) )
+            goto fail;
+        printf("okay\n");
+
+        printf("%-40s", "Testing shrd $8,%ecx,(%rdi),%ecx...");
+        instr[2] = 0x74; instr[4] = 0x2c; instr[5] = 0x0f; instr[6] = 0x08;
+        *res        = 0x22334455;
+        regs.eflags = EFLAGS_ALWAYS_SET | X86_EFLAGS_CF;
+        regs.rip    = (unsigned long)&instr[0];
+        regs.ecx    = 0x44332211;
+        regs.rdi    = (unsigned long)res;
+        rc = x86_emulate(&ctxt, &emulops);
+        if ( (rc != X86EMUL_OKAY) ||
+             (regs.rcx != 0x11223344) ||
+             (*res != 0x22334455) ||
+             ((regs.eflags & (EFLAGS_MASK & ~X86_EFLAGS(OF, AF)))
+              != (EFLAGS_ALWAYS_SET | X86_EFLAGS_PF)) ||
+             (regs.rip != (unsigned long)&instr[7]) )
+            goto fail;
+        printf("okay\n");
+
+        printf("%-40s", "Testing shld $1,%ecx,(%rdx),%edx...");
+        *res        = 0x12345678;
+        regs.ecx    = 0x9abcdef0;
+        instr[2] = 0x6c; instr[4] = 0x24; instr[5] = 0x0a; instr[6] = 0x01;
+        for ( ; ; )
+        {
+            uint32_t r = res[0];
+            const uint32_t m = X86_EFLAGS_ARITH_MASK & ~X86_EFLAGS_AF;
+            unsigned long f;
+
+            regs.rdx    = (unsigned long)res;
+            asm ( "shld $1,%2,%0; pushf; pop %1"
+                  : "+rm" (r), "=rm" (f) : "r" ((uint32_t)regs.ecx) );
+            regs.eflags = f ^ m;
+            regs.rip    = (unsigned long)&instr[0];
+            rc = x86_emulate(&ctxt, &emulops);
+            if ( (rc != X86EMUL_OKAY) ||
+                 (regs.rdx != r) ||
+                 (*res != 0x12345678) ||
+                 ((regs.eflags ^ f) & m) ||
+                 (regs.rip != (unsigned long)&instr[7]) )
+                goto fail;
+            if ( !regs.ecx )
+                break;
+            regs.ecx <<= 1;
+        }
+        printf("okay\n");
+
         printf("%-40s", "Testing dec %cx,%ax...");
         instr[2] = 0x7d; instr[4] = 0xff; instr[5] = 0xc9;
         regs.eflags = EFLAGS_ALWAYS_SET;
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -623,6 +623,12 @@ static const struct map4_table {
         [vex_np] = { .nd = true, .nf = true, .nci_ndd_nf = true },
         [vex_66] = { .nd = true, .nf = true, .nci_ndd_nf = true },
     },
+    [0x24] = { /* SHLD */
+        [vex_np] = { .to_mem = true, .imm8 = true, .nd = true, .nf = true,
+                     .nci_ndd_nf = true },
+        [vex_66] = { .to_mem = true, .imm8 = true, .nd = true, .nf = true,
+                     .nci_ndd_nf = true },
+    },
     [0x28] = { /* SUB (byte) */
         [vex_np] = { .to_mem = true, .byte = true, .nd = true, .nf = true,
                      .nci_ndd_nf = true },
@@ -641,6 +647,12 @@ static const struct map4_table {
         [vex_np] = { .nd = true, .nf = true, .nci_ndd_nf = true },
         [vex_66] = { .nd = true, .nf = true, .nci_ndd_nf = true },
     },
+    [0x2c] = { /* SHRD */
+        [vex_np] = { .to_mem = true, .imm8 = true, .nd = true, .nf = true,
+                     .nci_ndd_nf = true },
+        [vex_66] = { .to_mem = true, .imm8 = true, .nd = true, .nf = true,
+                     .nci_ndd_nf = true },
+    },
     [0x30] = { /* XOR (byte) */
         [vex_np] = { .to_mem = true, .byte = true, .nd = true, .nf = true,
                      .nci_ndd_nf = true },
@@ -675,6 +687,50 @@ static const struct map4_table {
         [vex_66] = { .to_mem = true, .imm8 = true, .nd = true,
                      .nci_ndd_nf = true },
     },
+    [0xa5] = { /* SHLD */
+        [vex_np] = { .to_mem = true, .nd = true, .nf = true,
+                     .nci_ndd_nf = true },
+        [vex_66] = { .to_mem = true, .nd = true, .nf = true,
+                     .nci_ndd_nf = true },
+    },
+    [0xad] = { /* SHRD */
+        [vex_np] = { .to_mem = true, .nd = true, .nf = true,
+                     .nci_ndd_nf = true },
+        [vex_66] = { .to_mem = true, .nd = true, .nf = true,
+                     .nci_ndd_nf = true },
+    },
+    [0xc0] = { /* Grp2 (byte, imm8); .nf depends on modrm_reg */
+        [vex_np] = { .to_mem = true, .byte = true, .imm8 = true, .nd = true,
+                     .nci_ndd_nf = true },
+        [vex_66] = { .to_mem = true, .byte = true, .imm8 = true, .nd = true,
+                     .nci_ndd_nf = true },
+    },
+    [0xc1] = { /* Grp2 ({,d,q}word, imm8); .nf depends on modrm_reg */
+        [vex_np] = { .to_mem = true, .imm8 = true, .nd = true,
+                     .nci_ndd_nf = true },
+        [vex_66] = { .to_mem = true, .imm8 = true, .nd = true,
+                     .nci_ndd_nf = true },
+    },
+    [0xd0] = { /* Grp2 (byte, 1); .nf depends on modrm_reg */
+        [vex_np] = { .to_mem = true, .byte = true, .nd = true,
+                     .nci_ndd_nf = true },
+        [vex_66] = { .to_mem = true, .byte = true, .nd = true,
+                     .nci_ndd_nf = true },
+    },
+    [0xd1] = { /* Grp2 ({,d,q}word, 1); .nf depends on modrm_reg */
+        [vex_np] = { .to_mem = true, .nd = true, .nci_ndd_nf = true },
+        [vex_66] = { .to_mem = true, .nd = true, .nci_ndd_nf = true },
+    },
+    [0xd2] = { /* Grp2 (byte, %cl); .nf depends on modrm_reg */
+        [vex_np] = { .to_mem = true, .byte = true, .nd = true,
+                     .nci_ndd_nf = true },
+        [vex_66] = { .to_mem = true, .byte = true, .nd = true,
+                     .nci_ndd_nf = true },
+    },
+    [0xd3] = { /* Grp2 ({,d,q}word, %cl); .nf depends on modrm_reg */
+        [vex_np] = { .to_mem = true, .nd = true },
+        [vex_66] = { .to_mem = true, .nd = true },
+    },
     [0xf6] = { /* Grp3 (byte); most attributes depend on modrm_reg */
         [vex_np] = { .byte = true, .nci_ndd_nf = true },
     },
@@ -1222,6 +1278,11 @@ decode_map4(struct x86_emulate_state *s,
         nf = map4_table[(s->modrm_reg & 7) << 3][s->evex.pfx].nf;
         break;
 
+    case 0xc0: case 0xc1: case 0xd0 ... 0xd3: /* Grp2 */
+        /* rcl/rcr do not allow EVEX.nf to be set. */
+        nf = (s->modrm_reg & 6) != 2;
+        break;
+
     case 0xf6: case 0xf7: /* Grp3 */
         switch ( s->modrm_reg & 7 )
         {
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -2442,14 +2442,19 @@ x86_emulate(
         dst.val = src.val;
         break;
 
-    case 0xc0 ... 0xc1: grp2: /* Grp2 */
+    case 0xc0 ... 0xc1: /* Grp2 */
+    case X86EMUL_OPC_EVEX   (4, 0xc0): /* <op> imm8,r/m{,r8} */
+    case X86EMUL_OPC_EVEX   (4, 0xc1): /* <op> imm8,r/m{,reg} */
+    case X86EMUL_OPC_EVEX_66(4, 0xc1): /* <op> imm8,r/m{,r16} */
+    grp2:
         generate_exception_if(lock_prefix, X86_EXC_UD);
 
         switch ( modrm_reg & 7 )
         {
 #define GRP2(name, ext) \
         case ext: \
-            if ( ops->rmw && dst.type == OP_MEM ) \
+            if ( ops->rmw && dst.type == OP_MEM && \
+                 (!evex_encoded() || !EVEX_ND(&evex)) ) \
                 state->rmw = rmw_##name; \
             else \
                 emulate_2op_SrcB(#name, src, dst, _regs.eflags); \
@@ -2609,10 +2614,16 @@ x86_emulate(
     }
 
     case 0xd0 ... 0xd1: /* Grp2 */
+    case X86EMUL_OPC_EVEX   (4, 0xd0): /* <op> $1,r/m{,r8} */
+    case X86EMUL_OPC_EVEX   (4, 0xd1): /* <op> $1,r/m{,reg} */
+    case X86EMUL_OPC_EVEX_66(4, 0xd1): /* <op> $1,r/m{,r16} */
         src.val = 1;
         goto grp2;
 
     case 0xd2 ... 0xd3: /* Grp2 */
+    case X86EMUL_OPC_EVEX   (4, 0xd2): /* <op> %cl,r/m{,r8} */
+    case X86EMUL_OPC_EVEX   (4, 0xd3): /* <op> %cl,r/m{,reg} */
+    case X86EMUL_OPC_EVEX_66(4, 0xd3): /* <op> %cl,r/m{,r16} */
         src.val = _regs.cl;
         goto grp2;
 
@@ -5335,7 +5346,15 @@ x86_emulate(
     case X86EMUL_OPC(0x0f, 0xa4): /* shld imm8,r,r/m */
     case X86EMUL_OPC(0x0f, 0xa5): /* shld %%cl,r,r/m */
     case X86EMUL_OPC(0x0f, 0xac): /* shrd imm8,r,r/m */
-    case X86EMUL_OPC(0x0f, 0xad): /* shrd %%cl,r,r/m */ {
+    case X86EMUL_OPC(0x0f, 0xad): /* shrd %%cl,r,r/m */
+    case X86EMUL_OPC_EVEX   (4, 0x24): /* shld imm8,r/m{,reg} */
+    case X86EMUL_OPC_EVEX_66(4, 0x24): /* shld imm8,r/m{,r16} */
+    case X86EMUL_OPC_EVEX   (4, 0x2c): /* shrd imm8,r/m{,reg} */
+    case X86EMUL_OPC_EVEX_66(4, 0x2c): /* shrd imm8,r/m{,r16} */
+    case X86EMUL_OPC_EVEX   (4, 0xa5): /* shld %cl,r/m{,reg} */
+    case X86EMUL_OPC_EVEX_66(4, 0xa5): /* shld %cl,r/m{,r16} */
+    case X86EMUL_OPC_EVEX   (4, 0xad): /* shrd %cl,r/m{,reg} */
+    case X86EMUL_OPC_EVEX_66(4, 0xad): /* shrd %cl,r/m{,r16} */ {
         uint8_t shift;
 
         generate_exception_if(lock_prefix, X86_EXC_UD);
@@ -5349,7 +5368,8 @@ x86_emulate(
             src.val = truncate_word(*src.reg, dst.bytes);
         }
 
-        if ( ops->rmw && dst.type == OP_MEM )
+        if ( ops->rmw && dst.type == OP_MEM &&
+             (!evex_encoded() || !EVEX_ND(&evex)) )
         {
             ea.orig_val = shift;
             state->rmw = b & 8 ? rmw_shrd : rmw_shld;

 

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