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[PATCH 03/30] x86/xstate: enable APX_F


  • To: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Wed, 11 Nov 2026 15:21:40 +0100
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  • Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Teddy Astie <teddy.astie@xxxxxxxxxx>, Roger Pau Monné <roger@xxxxxxxxxxxxxx>
  • Delivery-date: Wed, 11 Nov 2026 14:21:44 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

Add / adjust basic definitions. Adjust recalculate_xstate() and
xstate_check_sizes() accordingly.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -220,6 +220,9 @@ static void recalculate_xstate(struct cp
     if ( p->feat.amx_tile )
         xstates |= X86_XCR0_TILE_CFG | X86_XCR0_TILE_DATA;
 
+    if ( p->feat.apx_f )
+        xstates |= X86_XCR0_APX;
+
     /* Subleaf 0 */
     p->xstate.max_size =
         xstate_uncompressed_size(xstates & ~XSTATE_XSAVES_ONLY);
--- a/xen/arch/x86/include/asm/cpufeature.h
+++ b/xen/arch/x86/include/asm/cpufeature.h
@@ -220,6 +220,9 @@ static inline bool boot_cpu_has(unsigned
 #define cpu_has_verw_clear      boot_cpu_has(X86_FEATURE_VERW_CLEAR)
 #define cpu_has_nscb            boot_cpu_has(X86_FEATURE_NSCB)
 
+/* CPUID level 0x00000007:1.edx */
+#define cpu_has_apx_f           boot_cpu_has(X86_FEATURE_APX_F)
+
 /* MSR_ARCH_CAPS */
 #define cpu_has_rdcl_no         boot_cpu_has(X86_FEATURE_RDCL_NO)
 #define cpu_has_eibrs           boot_cpu_has(X86_FEATURE_EIBRS)
--- a/xen/arch/x86/include/asm/x86-defns.h
+++ b/xen/arch/x86/include/asm/x86-defns.h
@@ -109,13 +109,14 @@
 #define X86_XSS_HWP               (_AC(1, ULL) << 16)
 #define X86_XCR0_TILE_CFG         (_AC(1, ULL) << 17)
 #define X86_XCR0_TILE_DATA        (_AC(1, ULL) << 18)
+#define X86_XCR0_APX              (_AC(1, ULL) << 19)
 #define X86_XCR0_LWP              (_AC(1, ULL) << 62)
 
 #define X86_XCR0_STATES                                                 \
     (X86_XCR0_X87 | X86_XCR0_SSE | X86_XCR0_YMM | X86_XCR0_BNDREGS |    \
      X86_XCR0_BNDCSR | X86_XCR0_OPMASK | X86_XCR0_ZMM |                 \
      X86_XCR0_HI_ZMM | X86_XCR0_PKRU | X86_XCR0_TILE_CFG |              \
-     X86_XCR0_TILE_DATA |                                               \
+     X86_XCR0_TILE_DATA | X86_XCR0_APX |                                \
      X86_XCR0_LWP)
 
 #define X86_XSS_STATES                                                  \
--- a/xen/arch/x86/include/asm/xstate.h
+++ b/xen/arch/x86/include/asm/xstate.h
@@ -34,7 +34,7 @@ extern uint32_t mxcsr_mask;
 #define XCNTXT_MASK    (X86_XCR0_X87 | X86_XCR0_SSE | X86_XCR0_YMM | \
                         X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM | \
                         X86_XCR0_BNDREGS | X86_XCR0_BNDCSR | X86_XCR0_PKRU | \
-                        X86_XCR0_TILE_CFG | X86_XCR0_TILE_DATA)
+                        X86_XCR0_TILE_CFG | X86_XCR0_TILE_DATA | X86_XCR0_APX)
 
 #define XSTATE_ALL     (~(1ULL << 63))
 #define XSTATE_XSAVES_ONLY         0
--- a/xen/arch/x86/xstate.c
+++ b/xen/arch/x86/xstate.c
@@ -847,6 +847,9 @@ static void __init noinline xstate_check
     if ( boot_cpu_has(X86_FEATURE_AMX_TILE) )
         check_new_xstate(&s, X86_XCR0_TILE_DATA | X86_XCR0_TILE_CFG);
 
+    if ( cpu_has_apx_f )
+        check_new_xstate(&s, X86_XCR0_APX);
+
     if ( boot_cpu_has(X86_FEATURE_LWP) )
         check_new_xstate(&s, X86_XCR0_LWP);
 




 


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