[PATCH v5 19/19] x86emul: support AVX10.2-aux PS <-> {B,H}F8{,S} converts

[Jan Beulich <jbeulich@xxxxxxxx>]

Their handling again follows that of other convert insns.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
SDE: ???
---
v5: New.

--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -18,6 +18,7 @@ The format is based on [Keep a Changelog
 ### Added
  - On x86:
    - Support for AVX10.2. (Experimental)
+   - Support for AVX10-V2-AUX. (Experimental)
 
 ### Removed
  - On Arm:
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -830,9 +830,21 @@ static const struct test avx10_2_aux_all
 //       cvtbf62hf8,     66, map5, 37,   vl,    w, vl
     INSN(cvtbf82bf4s,    f3, map5, 3d, vl_2,    b, vl),
 //       cvtbf82bf6s,    f3, map5, 3e,   vl,    w, vl
+    INSN(cvtbf82ps,        , map5, 36, vl_4,    w, vl),
+    INSN(cvtbiasps2hf8,    , map5, 38,   vl,    d, vl),
+    INSN(cvtbiasps2bf8,    , map5, 39,   vl,    d, vl),
+    INSN(cvtbiasps2hf8s,   , map5, 3a,   vl,    d, vl),
+    INSN(cvtbiasps2bf8s,   , map5, 3b,   vl,    d, vl),
 //       cvthf62hf8,     66, map5, 37,   vl,    b, vl
     INSN(cvthf82bf4s,    f3, map5, 3d, vl_2,    w, vl),
 //       cvthf82hf6s,    f3, map5, 3e,   vl,    b, vl
+    INSN(cvthf82ps,        , map5, 36, vl_4,    b, vl),
+    INSN(cvtps2hf8,      f3, map5, 38,   vl,    d, vl),
+    INSN(cvtps2bf8,      f3, map5, 39,   vl,    d, vl),
+    INSN(cvtps2hf8s,     f3, map5, 3a,   vl,    d, vl),
+    INSN(cvtps2bf8s,     f3, map5, 3b,   vl,    d, vl),
+    INSN(cvtrops2hf8,    66, map5, 38,   vl,    d, vl),
+    INSN(cvtrops2hf8s,   66, map5, 3a,   vl,    d, vl),
     INSN(pmovssdb,       f3, 0f38, 41, vl_4,    b, vl),
     INSN(unpackb,          , 0f3a, 3d,   vl,    b, vl),
 };
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -2147,8 +2147,19 @@ static const struct evex {
     { { 0x2f }, 2, T, R, pfx_no, W0, LIG }, /* vcomish */
     { { 0x2f }, 2, T, R, pfx_66, W0, LIG }, /* vcomisbf16 */
     { { 0x2f }, 2, T, R, pfx_f3, W0, LIG }, /* vcomxsh */
+    { { 0x36 }, 2, T, R, pfx_no, Wn, Ln }, /* vcvt{b,h}f82ps */
     { { 0x37 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbf42hf8 */
     { { 0x37, 0xc0 }, 2, F, N, pfx_66, Wn, Ln }, /* vcvt{b,h}f62hf8 */
+    { { 0x38 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasps2hf8 */
+    { { 0x38 }, 2, T, R, pfx_66, W0, Ln }, /* vcvtrops2hf8 */
+    { { 0x38 }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtps2hf8 */
+    { { 0x39 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasps2bf8 */
+    { { 0x39 }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtps2bf8 */
+    { { 0x3a }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasps2hf8s */
+    { { 0x3a }, 2, T, R, pfx_66, W0, Ln }, /* vcvtrops2hf8s */
+    { { 0x3a }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtps2hf8s */
+    { { 0x3b }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasps2bf8s */
+    { { 0x3b }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtps2bf8s */
     { { 0x3c, 0xc0 }, 2, F, N, pfx_f3, W0, Ln }, /* vcvthf82hf6s */
     { { 0x3d }, 2, T, W, pfx_f3, Wn, Ln }, /* vcvt{b,h}f82bf4s */
     { { 0x3e, 0xc0 }, 2, F, N, pfx_f3, W1, Ln }, /* vcvtbf82bf6s */
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -1254,9 +1254,10 @@ int x86emul_decode(struct x86_emulate_st
                         /*
                          * Re-use twobyte_table[] here, for the similarity of
                          * the entries valid in map 5.  There's always a
-                         * ModR/M byte, though.
+                         * ModR/M byte, though, and never an immediate.
                          */
-                        d = twobyte_table[b].desc | ModRM;
+                        d = (twobyte_table[b].desc | ModRM) &
+                            ~(SrcImmByte | SrcImm);
                         s->simd_size = twobyte_table[b].size ?: simd_other;
                         break;
 
@@ -1626,6 +1627,21 @@ int x86emul_decode(struct x86_emulate_st
                 disp8scale = 3 + s->evex.lr;
                 break;
 
+            case 0x36: /* vcvt{b,h}f82ps */
+                d = DstReg | SrcMem | TwoOp;
+                disp8scale = 2 + s->evex.lr;
+                break;
+
+            case 0x38: /* vcvt{,bias,ro}ps2hf8 */
+            case 0x39: /* vcvt{,bias}ps2bf8 */
+            case 0x3a: /* vcvt{,bias,ro}ps2hf8s */
+            case 0x3b: /* vcvt{,bias}ps2bf8s */
+                d = DstReg | SrcMem;
+                if ( s->evex.pfx )
+                    d |= TwoOp;
+                disp8scale = s->evex.brs ? 2 : 4 + s->evex.lr;
+                break;
+
             case 0x3d: /* vcvt{b,h}f82hf4s */
                 d = DstMem | SrcReg | TwoOp;
                 disp8scale = 3 + s->evex.lr;
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -8039,6 +8039,13 @@ x86_emulate(
         op_bytes = 8 << evex.lr;
         goto simd_zmm;
 
+    case X86EMUL_OPC_EVEX(5, 0x36): /* vcvt{b,h}f82ps 
[xy]mm/m{32,64,128}[xyz]mm */
+        generate_exception_if(evex.brs, X86_EXC_UD);
+        vcpu_must_have(avx10_2_aux);
+        avx512_vlen_check(false);
+        op_bytes = 4 << evex.lr;
+        goto simd_zmm;
+
     case X86EMUL_OPC_EVEX_F3(5, 0x3d): /* vcvt{b,h}f82bf4s 
[xyz]mm,[xy]mm/m{64,128,256} */
         generate_exception_if(evex.opmsk, X86_EXC_UD);
         fallthrough;
@@ -8062,6 +8069,23 @@ x86_emulate(
         op_bytes = 1; /* Any non-zero value will do. */
         goto simd_zmm;
 
+    case X86EMUL_OPC_EVEX   (5, 0x38): /* vcvtbiasps2hf8 [xyz]mm/mem,xmm{k} */
+    case X86EMUL_OPC_EVEX_66(5, 0x38): /* vcvtrops2hf8 [xyz]mm/mem,xmm{k} */
+    case X86EMUL_OPC_EVEX_F3(5, 0x38): /* vcvtps2hf8 [xyz]mm/mem,xmm{k} */
+    case X86EMUL_OPC_EVEX   (5, 0x39): /* vcvtbiasps2bf8 [xyz]mm/mem,xmm{k} */
+    case X86EMUL_OPC_EVEX_F3(5, 0x39): /* vcvtps2bf8 [xyz]mm/mem,xmm{k} */
+    case X86EMUL_OPC_EVEX   (5, 0x3a): /* vcvtbiasps2hf8s [xyz]mm/mem,xmm{k} */
+    case X86EMUL_OPC_EVEX_66(5, 0x3a): /* vcvtrops2hf8s [xyz]mm/mem,xmm{k} */
+    case X86EMUL_OPC_EVEX_F3(5, 0x3a): /* vcvtps2hf8s [xyz]mm/mem,xmm{k} */
+    case X86EMUL_OPC_EVEX   (5, 0x3b): /* vcvtbiasps2bf8s [xyz]mm/mem,xmm{k} */
+    case X86EMUL_OPC_EVEX_F3(5, 0x3b): /* vcvtps2bf8s [xyz]mm/mem,xmm{k} */
+        generate_exception_if(evex.w || (ea.type != OP_MEM && evex.brs),
+                              X86_EXC_UD);
+        vcpu_must_have(avx10_2_aux);
+        avx512_vlen_check(false);
+        op_bytes = evex.brs ? 4 : 8 << evex.lr;
+        goto simd_zmm;
+
     case X86EMUL_OPC_EVEX_66(5, 0x51): /* vsqrtbf16 [xyz]mm/mem,[xyz]mm{k} */
     case X86EMUL_OPC_EVEX_66(5, 0x58): /* vaddbf16 
[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
     case X86EMUL_OPC_EVEX_66(5, 0x59): /* vmulbf16 
[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -412,7 +412,7 @@ XEN_CPUFEATURE(TSA_L1_NO,          18*32
 /* x86-ecosystem-defined CPU features, CPUID level 0x00000024:1.ecx, word 19 */
 XEN_CPUFEATURE(AVX10_BMM,          19*32+ 1) /*   AVX10-BMM Instructions */
 XEN_CPUFEATURE(AVX10_V1_AUX,       19*32+ 2) /*a  AVX10 V1 Auxiliary 
Instructions */
-XEN_CPUFEATURE(AVX10_V2_AUX,       19*32+ 3) /*   AVX10 V2 Auxiliary 
Instructions */
+XEN_CPUFEATURE(AVX10_V2_AUX,       19*32+ 3) /*a  AVX10 V2 Auxiliary 
Instructions */
 
 #endif /* XEN_CPUFEATURE */