[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v13 02/14] xen/arm: gic-v2: Implement GIC suspend/resume functions
- To: Mykola Kvach <mykola_kvach@xxxxxxxx>
- From: Bertrand Marquis <Bertrand.Marquis@xxxxxxx>
- Date: Tue, 10 Nov 2026 14:27:26 +0000
- Accept-language: en-GB, en-US
- Arc-authentication-results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=epam.com smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com])
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=apPZTgNbjxmMpmw/gs1ts/8hwGrfpXWfH8+SDYRpMXs=; b=s0nBmOn1qB6urfs2BYINF9Ar39atIh4/aM5zcf7r5QNFSkl3B/q3Cmdjl02ZPuttJqurDxFz+X70yu9+7O0UgdA/YFa5Ar5TeXD49UgxbhQtYq38B/oV2do6WSgUFTItZzPJ3opPWjh4I1aEbn/Ou6Y5U8nQd4tpsBUU/L/3EnZOz5tqP/5sKPKy89QUsV5k6RJUqK3x0V13K1Hf2nM3ULHRah4RuHuwoCkbfkWo+1ggJKPb5PDg2rl45/RE8WD/UpnDkfZ01fCw+6MUiwqZAgmIOglxbpWbnJ3Sqr9H4J9xmBPqwno+JL//Ma+2GRvA5iVCnpvtQyQZIyEfkVhk5Q==
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=apPZTgNbjxmMpmw/gs1ts/8hwGrfpXWfH8+SDYRpMXs=; b=jVC3pjP5V0lo8V3I4SkOszf14lXnbjsopMyzTNDRe9u0SbsWquaDqJhTpWM7Da9XwOAIdQ0NVkCxVgI8zSnNDtrpp8JF/VREkoyMgqWqvScg6SPbNgm8foEkyvnxL/PX6r0/xSVyM8MVdw954C7qz73id+xHhZtTYDJx1wNqmy18+kkatQxHPyDvXvMRUClqZTSdDX5lhg/uhEqbW2Gqw3b4WncoWBfUMk3NN/WDsD3BP92lh7Mt3DvgfLo978zFpGUTzsV6JrTF5fZTF+SpJC4p/8BG7GJd1dQbnzfsQH0A+Pg2FTPb3U+v9yrwrADmlSCXLBWEpBeRf461sEQ7sQ==
- Arc-seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=f2Rc7D0GYPrXSBKj4n2NGFDVPZw4N55eoGlB2X/zeX29XJY0ryASyzBhAZNaTmQ9Wv+kyzElQg4a8+3MoieNd8JYwiOr2ncuaSJMWHXUdDbTBb0BCtjrz0NAUKQizmgCVJ8gbtqpIj5i1480KiivQLgm7liR8B+JIGQKnnD91e0A6KpEWfIsm6lgjSUWdBuM7+43Cp+0Gi7ObyL03v2fDHfHxJmbogBte9tVcXgDva5TUiPL6hiz9H/XPI17NYeFnuJ1mU6ohjhecfUPDB4c69j1aC15s72TPnL1X4bX5aAjkX8HSU5Q5WYzaC/WULQAMYCOio7NfRMgM9rm7+9yKw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=V+sHLTUpl0EBC9Mriqp0ZUq9jWlJ9JwG8GRCarsGk9YwyZi8MAMDm52Sxn06o0PSfwZjTYXf3fZW5VG44zqDbAK/IpFVLzA9m/1CMtPwgRSP4d4m7QOfyWkS5KvyBNRcdOCsgBKVLp8zZ7joxqQiinP5LKdIDIoexegloouEnDLo3fCtZscmVNFZ52zmFmJFU+QROh+PsoHCZyQMggMSZNPvzkS4pJjUQNQvYhtIdrxh7e759fHaPCzAgtLqY4OLxF5sMY33VZOIWvScTE1/L8Qi/FfofUXbr7riJtkfBYDAEbhvZ7bam1ZlAghZyZ1k8330YJi6uGqRhjl8BJeXUA==
- Authentication-results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=arm.com header.i="@arm.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck"; dkim=pass header.s=selector1 header.d=arm.com header.i="@arm.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck"
- Authentication-results-original: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Mirela Simonovic <mirela.simonovic@xxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, Saeed Nowshadi <saeed.nowshadi@xxxxxxxxxx>, Mykyta Poturai <mykyta_poturai@xxxxxxxx>
- Delivery-date: Tue, 10 Nov 2026 14:28:18 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Nodisclaimer: true
- Thread-index: AQHdZlcGwNOcdJs5ak+RYvHufcw5obcncnyA
- Thread-topic: [PATCH v13 02/14] xen/arm: gic-v2: Implement GIC suspend/resume functions
Hi Mykola,
> On 27 Oct 2026, at 22:05, Mykola Kvach <mykola_kvach@xxxxxxxx> wrote:
>
> From: Mirela Simonovic <mirela.simonovic@xxxxxxxxxx>
>
> System suspend may lead to a state where GIC would be powered down.
> Therefore, Xen should save/restore the context of GIC on suspend/resume.
>
> Note that the context consists of states of registers which are
> controlled by the hypervisor. Other GIC registers which are accessible
> by guests are saved/restored on context switch.
>
> Do not save or restore physical pending interrupt state, including
> SGIs and PPI/SPI pending bits in GICD_ISPENDR. Before this point, device
> drivers must stop normal I/O and quiesce non-wakeup interrupt sources.
> Earlier events must have been handled or remain recorded outside the
> GIC. The platform must preserve wakeup events throughout suspend entry
> and sleep if the GIC loses state. Level sources still asserted after
> resume become pending again. Edge events need state retained outside
> the GIC; saving GICD_ISPENDR would not cover events arriving after the
> read.
>
> Keep the Distributor and CPU interface control state unchanged during
> suspend entry. GICv2 wakeup signals depend on Distributor group enables,
> and firmware may check pending interrupts through the CPU interface
> before accepting SYSTEM_SUSPEND. Leave shutdown and wakeup setup to
> firmware. Disable the interfaces while restoring their state on resume.
>
> CPU-interface active-priority state is not restored. Xen enters this
> path with local IRQs disabled and must have no active-priority context
> to replay after resume. If any visible GICC_APRn bit is still set,
> abort suspend with -EBUSY without changing the GIC control registers.
>
> This does not apply to distributor active state. With GICv2 EOImode==1,
> EOIR only drops the interrupt priority; final deactivation is a separate
> step. For guest-routed interrupts, Xen can have already EOIed the physical
> IRQ while deactivation is still pending on the vGIC/GICV path. Therefore
> GICD_ISACTIVER is preserved as architectural in-flight interrupt state.
>
> Signed-off-by: Mirela Simonovic <mirela.simonovic@xxxxxxxxxx>
> Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xxxxxxxxxx>
> Signed-off-by: Mykyta Poturai <mykyta_poturai@xxxxxxxx>
> Signed-off-by: Mykola Kvach <mykola_kvach@xxxxxxxx>
Thanks for the added comments for PPI/SPI handling.
Reviewed-by: Bertrand Marquis <bertrand.marquis@xxxxxxx>
Cheers
Bertrand
|
