From c5521dbadd1814aeab64378711a33ed52b978557 Mon Sep 17 00:00:00 2001 From: Julien Grall Date: Tue, 24 Jan 2023 19:26:29 +0000 Subject: xen/arm: flushtlb: Reduce scope of barrier for the TLB range flush At the moment, flush_xen_tlb_range_va{,_local}() are using system wide memory barrier. This is quite expensive and unnecessary. For the local version, a non-shareable barrier is sufficient. For the SMP version, an inner-shareable barrier is sufficient. Furthermore, the initial barrier only needs to a store barrier. For the full explanation of the sequence see asm/arm{32,64}/flushtlb.h. Signed-off-by: Julien Grall Reviewed-by: Michal Orzel Reviewed-by: Henry Wang (cherry picked from commit 5e5d1a43e18468399448ff8dec687342d48f56da) diff --git a/xen/arch/arm/include/asm/flushtlb.h b/xen/arch/arm/include/asm/flushtlb.h index 125a141975e0..e45fb6d97b02 100644 --- a/xen/arch/arm/include/asm/flushtlb.h +++ b/xen/arch/arm/include/asm/flushtlb.h @@ -37,13 +37,14 @@ static inline void flush_xen_tlb_range_va_local(vaddr_t va, { vaddr_t end = va + size; - dsb(sy); /* Ensure preceding are visible */ + /* See asm/arm{32,64}/flushtlb.h for the explanation of the sequence. */ + dsb(nshst); /* Ensure prior page-tables updates have completed */ while ( va < end ) { __flush_xen_tlb_one_local(va); va += PAGE_SIZE; } - dsb(sy); /* Ensure completion of the TLB flush */ + dsb(nsh); /* Ensure the TLB invalidation has completed */ isb(); } @@ -56,13 +57,14 @@ static inline void flush_xen_tlb_range_va(vaddr_t va, { vaddr_t end = va + size; - dsb(sy); /* Ensure preceding are visible */ + /* See asm/arm{32,64}/flushtlb.h for the explanation of the sequence. */ + dsb(ishst); /* Ensure prior page-tables updates have completed */ while ( va < end ) { __flush_xen_tlb_one(va); va += PAGE_SIZE; } - dsb(sy); /* Ensure completion of the TLB flush */ + dsb(ish); /* Ensure the TLB invalidation has completed */ isb(); }