[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH] xen/arm: gic-v3: Wait for redistributor RWP using the right bit
- To: Mykola Kvach <xakep.amatop@xxxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: "Orzel, Michal" <michal.orzel@xxxxxxx>
- Date: Mon, 18 May 2026 06:40:19 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=gmail.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0)
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jUYfxPpATFHSXkm6dLvUWLUHw5eYI30x3dRwJHoN4Vg=; b=d92rwK3IxsUw3hCHLnluyLqh2qCOy5Gr4uey+QaTbEnhaslFC0NjGKTpM3yXoMoxREySt1Revexc5sD+qhehyWx7gazmbavXCKPm6XNYN3re7uOBSDP+2f+OyCAw8kMII2Dj5+SJR7Swv9/8MUNO/EgTl3JEtIY5005Vve6WhBooV6FKAtc4tCk7scmUgJNJ2GEswb2Ta02lyUIv9exvnU/Hx7ScMBCcoMYieLtnKTq4v5VRM5MIEebJcoDwQhHSXkXAVXu1jKgWAFdfC5zZ7iIwGT8tvm1AEoCxfFHp1zVlHk1FZAH7ip/rFozrnFNAzNoRrHUVOSsiMjS8tmKlPw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ABOy49aWMeDVnRc4M/F2A6MnoQePoQC2KEpHddd77cPZBpnCSkVihDkx7jKdJAp18obr5oQYgiShhknFB2l1fnrAPNuP2wzsCeH2T3JyPOpUT37xAxlkCAmJzlSFiwzHpxEcO4dI3s0uDJh0OLWRZfdgt4vpJ4hxdPhnXsqpvicb9Lt4IeN7YqTqOoTe8nSMRZ6oZv/EYJxxG1pAmH4GT0c+fnS2EOgmGscJN04AZh93QwN9iXUWt7dxABjQlksP6l6ubGvtC81G9OaDMhZoLfAbDWh9oeVCDliADsSXCNxe2oqsPVhA9eFwVQ1+sIj5bcWdc4T+qof5knm2m60Hmg==
- Authentication-results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=amd.com header.i="@amd.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck"
- Cc: Mykola Kvach <mykola_kvach@xxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, Luca Fancellu <luca.fancellu@xxxxxxx>
- Delivery-date: Mon, 18 May 2026 04:40:49 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 14-May-26 11:08, Mykola Kvach wrote:
> From: Mykola Kvach <mykola_kvach@xxxxxxxx>
>
> gicv3_do_wait_for_rwp() is used for both distributor and
> redistributor writes. The CTLR register is at offset 0 for both,
> but the RWP bit is not in the same position.
>
> For GICD_CTLR, RWP is bit 31. For GICR_CTLR, bit 31 is UWP,
> while RWP is bit 3. The redistributor wait path was therefore
> polling UWP instead of RWP.
>
> UWP covers upstream writes, including Generate SGI packets, and is
> not a substitute for redistributor register write completion. The
> existing redistributor callers need RWP semantics for redistributor
> register writes such as GICR_ICENABLER0 and GICR_CTLR updates.
>
> Add GICR_CTLR_RWP and pass the expected RWP bit to the shared
> helper.
>
> Fixes: bc183a0235e ("xen/arm: Add support for GIC v3")
> Reported-by: Luca Fancellu <luca.fancellu@xxxxxxx>
> Signed-off-by: Mykola Kvach <mykola_kvach@xxxxxxxx>
Good, now it matches what Linux did a few years ago:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0df6664
Reviewed-by: Michal Orzel <michal.orzel@xxxxxxx>
~Michal
|
