[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 4/8] x86: replace APERFMPERF synthetic feature bit
- To: Jan Beulich <jbeulich@xxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Tue, 18 Nov 2025 15:41:03 +0000
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=t6o8tfdzHVkljlOcBbHO9NiT0V8NpQDoJXBAnUHjZec=; b=oHHed99ancESIT8DVO9ELSZM6e6Y4r3anU4rE2B32cCU5XLNG2idcVB2TCoBoS/7MGnfOoi6sKK0il6PXIOzwVaq2ITB1oNtoM5sWZDPuE2v6h04Lcx/fUBfCVhN5Q5YESfISCjhiFuBLsmWFlGEsoQ/GrfOJNt4GcNVxBrb0TIAAec+F1M+/CUXL+s9gL0SM9ZL6fi+5iTEQxN/Wjy+50ZfJof9BWN0vKvdNAuLTrE9GcAQAlRWtgTfwEkQWTjsv95nEwqdI+O0I4QtrdOQ2bYVhtY/OcX/35jZr+X4N/xTNlubCwafUHcA6SiVzF7+O+1HzvyKh3M2D0Ik/aOTqw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=iO8BVulEo0tCYSOFSLmAwNG4nE7OmT57aozorF1iuFGv+K3L8wdhFMisNtA5PdhYurcXOtu2VPtOgyrqeWHMOmn3qtxBMt8IOGAM86vP7xPHxPoI82VamJGWzYUWeFvpYMEtI7tmsYadcDQgXVSzklUcm61gDWURAJwcbBn2ynYE3isS0uXl3a1KNIq/YcGBnE8xXsE6iG/8yZQ08/c/rLzw50x2LGSBLwvWKA5QDDgjk2oo9xKPklkYCm9t0eW4h/q9OC97VCXAPKSh8ItpwFoZy6NksCQDAgZMrZkpVqlWDELQf9Gc55bvQ7LJUTPYfuM29xWHNbVpYG1KCSPS6Q==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com;
- Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Delivery-date: Tue, 18 Nov 2025 15:41:13 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 18/11/2025 3:07 pm, Jan Beulich wrote:
> Use the respective host CPU policy bit instead.
>
> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Right now, the synthetic features get levelled across the system. Now,
we take the BSP's copy.
This change is broadly fine, but it does need mentioning in the commit
message.
One thing we may want to do is take greater care to get the
masking/levelling MSRs properly level. Right now, if they're asymmetric
for any reason, we would previously end up using the common subset.
> --- a/xen/arch/x86/cpu/common.c
> +++ b/xen/arch/x86/cpu/common.c
> @@ -523,10 +523,6 @@ static void generic_identify(struct cpui
> if ( cpu_has(c, X86_FEATURE_CLFLUSH) )
> c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
>
> - if ( (c->cpuid_level >= CPUID_PM_LEAF) &&
> - (cpuid_ecx(CPUID_PM_LEAF) & CPUID6_ECX_APERFMPERF_CAPABILITY) )
> - __set_bit(X86_FEATURE_APERFMPERF, c->x86_capability);
> -
> /* AMD-defined flags: level 0x80000001 */
> if (c->extended_cpuid_level >= 0x80000001)
> cpuid(0x80000001, &tmp, &tmp,
> --- a/xen/arch/x86/include/asm/cpufeature.h
> +++ b/xen/arch/x86/include/asm/cpufeature.h
> @@ -11,7 +11,9 @@
> #include <xen/macros.h>
>
> #ifndef __ASSEMBLY__
> +#include <asm/cpu-policy.h>
> #include <asm/cpuid.h>
> +#include <xen/lib/x86/cpu-policy.h>
Why both?
~Andrew
|
