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Re: [XEN][PATCH] x86/hvm: vlapic: fix RO bits emulation in LVTx regs
- To: Jan Beulich <jbeulich@xxxxxxxx>, Grygorii Strashko <grygorii_strashko@xxxxxxxx>
- From: Alejandro Vallejo <alejandro.garciavallejo@xxxxxxx>
- Date: Fri, 26 Sep 2025 13:12:20 +0200
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Jason Andryuk <jason.andryuk@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Fri, 26 Sep 2025 11:12:41 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On Fri Sep 26, 2025 at 12:52 PM CEST, Jan Beulich wrote:
> On 26.09.2025 12:38, Grygorii Strashko wrote:
>> On 26.09.25 11:17, Jan Beulich wrote:
>>> On 25.09.2025 21:55, Grygorii Strashko wrote:
>>>> From: Grygorii Strashko <grygorii_strashko@xxxxxxxx>
>>>>
>>>> The LAPIC LVTx registers have two RO bits:
>>>> - all: Delivery Status (DS) bit 12
>>>> - LINT0/LINT1: Remote IRR Flag (RIR) bit 14.
>>>> This bit is reserved for other LVTx regs with RAZ/WI access type
>>>> (MMIO), while
>>>> WRMSR (guest_wrmsr_x2apic()) has appropiate checks for reserved bits
>>>> (MBZ access type).
>>>
>>> Question is what the behavior is for writing the r/o (but not reserved)
>>> bits.
>>> I wasn't able to find any statement in the SDM.
>>
>> Me too. Usually RO/WI on most HW.
>> For example, LAPIC MMIO "Write" will be ignored (WRMSR will trigger
>> exception).
>
> My remark was specifically about WRMSR, and what you say here contradicts ...
Not quite what you're asking, but writing to the X2APIC_ID register does trigger
#GP(0), so one would hope writing to RO bits triggers an exception too rather
than being WI when mixed with RW bits in a register.
Now again, it might not in order to avoid #GP(0) on a race.
Definitely worth running a silly test with wrmsr_safe() to make sure. I could
see real hardware going either way.
Cheers,
Alejandro
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